公开(公告)号：US11545221B2

公开(公告)日：2023-01-03

申请号：US17360572

申请日：2021-06-28

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

Abstract: Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

公开(公告)号：US20220406378A1

公开(公告)日：2022-12-22

申请号：US17350770

申请日：2021-06-17

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kazuki Isozumi ,  Parth Amin

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.

公开(公告)号：US20220404989A1

公开(公告)日：2022-12-22

申请号：US17349306

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G06F3/06

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

公开(公告)号：US20220383965A1

公开(公告)日：2022-12-01

申请号：US17329304

申请日：2021-05-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56

Abstract: To improve programming performance for a non-volatile memory , the verification of multiple programming levels can be performed based on a single discharge of a sensing capacitor through a selected memory cell by using different voltage levels on a second plate of the sensing capacitor: after discharging a first plate of the sensing capacitor through the selected memory cell, a result amount of charge is trapped on the first plate, which is then used to set first and second control gate voltages on a sensing transistor whose control gate is connected to the first place of the sensing capacitor based on respectively setting the second plate of the sensing capacitor to first and second voltage levels. To further improve programming performance, when the non-volatile memory stores in a multistate format, after the next to highest data state finishes programming, the next programming pulse can use a larger step size.

公开(公告)号：US20220328112A1

公开(公告)日：2022-10-13

申请号：US17229705

申请日：2021-04-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Jiahui Yuan ,  Abhijith Prakash

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/08

Abstract: Apparatuses and techniques are described for reducing damage to memory cells during single bit per cell programming. An initial program pulse in a single bit per cell program operation has a lower, first program level followed by a higher, second program level. As a result of the lower, first program level, the electric field across the memory cells is reduced. The step up time from the first program level to the second program level can be reduced by concurrently stepping up pass voltages of the adjacent unselected word lines. If an additional program pulse is applied, the step up in the program pulse can be omitted. The magnitude of the first program level can be adjusted based on factors such as temperature, number of program-erase cycles, selected sub-block position and selected word line position.

公开(公告)号：US11250926B2

公开(公告)日：2022-02-15

申请号：US16654696

申请日：2019-10-16

Applicant: SanDisk Technologies LLC

Inventor： Jianzhi Wu ,  Xiang Yang

IPC: G11C29/38 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C29/52 ,  G11C11/56 ,  G11C16/10 ,  G06F11/10

Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes memory cells arranged in sectors. Each of the memory cells includes a control gate in communication with one of a plurality of word lines and a drain coupled to one of a plurality of bit lines and is configured to retain a threshold voltage. A control circuit is in communication with the memory cells and is configured to read the threshold voltage of each of the memory cells using default read parameters. The control circuit determines whether reading the non-volatile memory cells using the default read parameters is successful. The control circuit dynamically tests and adjusts read parameters based on whether reading the memory cells using the read parameters is successful in response to determining that reading the memory cells using the default read parameters is not successful.

公开(公告)号：US11081179B2

公开(公告)日：2021-08-03

申请号：US16907639

申请日：2020-06-22

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/04 ,  G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/12 ,  G11C7/12

Abstract: Techniques are provided for pre-charging NAND strings during a programming operation. The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge phase of a programming operation, an overdrive voltage is applied to some memory cells and a bypass voltage is applied to other memory cells. The overdrive voltage allows the channel of an unselected NAND string to adequately charge during the pre-charge phase. Adequate charging of the channel helps the channel voltage to boost to a sufficient level to inhibit programming of an unselected memory cell during a program phase. Thus, program disturb is prevented, or at least reduced. The technique allows, for example, programming of memory cells in a middle vertical sub-block without causing program disturb of memory cells that are not to receive programming.

公开(公告)号：US11017869B2

公开(公告)日：2021-05-25

申请号：US16893626

申请日：2020-06-05

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/06 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.

公开(公告)号：US20210118518A1

公开(公告)日：2021-04-22

申请号：US16654696

申请日：2019-10-16

Applicant: SanDisk Technologies LLC

Inventor： Jianzhi Wu ,  Xiang Yang

IPC: G11C29/38 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C11/56 ,  G11C16/10 ,  G06F11/10 ,  G11C29/52

Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes memory cells arranged in sectors. Each of the memory cells includes a control gate in communication with one of a plurality of word lines and a drain coupled to one of a plurality of bit lines and is configured to retain a threshold voltage. A control circuit is in communication with the memory cells and is configured to read the threshold voltage of each of the memory cells using default read parameters. The control circuit determines whether reading the non-volatile memory cells using the default read parameters is successful. The control circuit dynamically tests and adjusts read parameters based on whether reading the memory cells using the read parameters is successful in response to determining that reading the memory cells using the default read parameters is not successful.

公开(公告)号：US10930355B2

公开(公告)日：2021-02-23

申请号：US16432142

申请日：2019-06-05

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/24 ,  G11C16/08 ,  G11C16/34 ,  G11C16/32

Abstract: A methodology and structure for accounting for fabrication difference in memory holes is described. Increasing the distance of the memory holes from the sources of etchant or other fabrication material results in different characteristics of the memory from the outer memory holes to the inner memory holes. These difference can be accounted for by grouping the memory holes and altering the parameters of the program or verify operations based on the groupings. The bitline voltage for the inner grouping can be less than the bitline voltage for the outer groupings. The sense timing can be greater for the outer groupings relative to the inner groupings. This can result in voltage threshold for the inner groupings and outer groupings overlying each other to improve memory performance.