公开(公告)号：US20170319907A1

公开(公告)日：2017-11-09

申请号：US15493792

申请日：2017-04-21

申请人： John Crawford

发明人： John Crawford

IPC分类号： A63B27/02 ,  F16B45/02 ,  A62B35/00

CPC分类号： A63B27/02 ,  A62B35/0037 ,  A62B35/0068 ,  E06C7/18 ,  E06C9/04 ,  F16B45/02

摘要： A support tower is equipped with a plurality of step-bolts, each of which comprises (1) a threaded portion that is attached to a pre-existing hole in the tower and (2) a shaft portion that extends outward from the tower. The shaft portion of each of the step-bolts includes an undercut section that is sized to match (with minimal clearance) the throat of a corresponding carabiner, which is attached to a safety harness worn by the user. The remainder of the shaft portion of the step-bolt is larger in diameter than the throat of the carabiner so that the carabiner cannot slide out toward the free end of the step-bolt.

公开(公告)号：US20090208285A1

公开(公告)日：2009-08-20

申请号：US11191251

申请日：2005-07-26

申请人： Richard S. Adler ,  John Crawford

发明人： Richard S. Adler ,  John Crawford

IPC分类号： E01F13/00

CPC分类号： E01F13/12 ,  E01F9/623 ,  E01F9/685 ,  E01F13/00

摘要： An anti-ram system and method of construction having a shallow mounted base pad from which extend a plurality of bollards. Very little or only a shallow excavation is required for the base of the bollard system, which can be partially or fully assembled prior to bringing it to the installation site. The shallow mounting pad or base of the bollard system of this invention may be formed or constructed in various ways and of various materials, and in various configurations. The shallow mounting pad or base is constructed so as to have considerable mass.

摘要翻译： 一种具有浅安装的基座的抗冲击系统和结构的方法，其中延伸有多个护柱。 护柱系统的底座需要很少的或只有一个浅层的挖掘，这可以在将其带到安装地点之前部分或完全组装。 本发明的护柱系统的浅安装垫或底座可以以各种方式和各种材料以各种构造形成或构造。 浅的安装垫或底座被构造成具有相当大的质量。

公开(公告)号：USD584438S1

公开(公告)日：2009-01-06

申请号：US29302841

申请日：2008-01-25

申请人： John Crawford ,  Donwoong Kang ,  Todd B. Abernethy ,  Scott W. Osiecki

设计人： John Crawford ,  Donwoong Kang ,  Todd B. Abernethy ,  Scott W. Osiecki

公开(公告)号：USD581567S1

公开(公告)日：2008-11-25

申请号：US29302837

申请日：2008-01-25

申请人： John Crawford ,  David J. Hine ,  Todd B. Abernethy ,  Donwoong Kang ,  Scott W. Osiecki

设计人： John Crawford ,  David J. Hine ,  Todd B. Abernethy ,  Donwoong Kang ,  Scott W. Osiecki

公开(公告)号：US20080074150A1

公开(公告)日：2008-03-27

申请号：US11856009

申请日：2007-09-14

申请人： John Crawford

发明人： John Crawford

IPC分类号： H03K19/082

CPC分类号： H03K19/01843 ,  H03K19/0826

摘要： A bidirectional signal transmission system including, a first bidirectional signal path having circuitry adapted to generate a logic high level on said first path, one or more first stations connected to the first bidirectional signal path adapted to monitor a logic level on said first path, and to generate a logic low level on said first path, an interface device operatively coupled to the first bi-directional signal path, said interface device having a first receive input also capable of functioning as an output capable of pulling the first path low; and a second bi-directional signal path coupled to a transmit output and a receive input on the buffered side of the interface device, said interface device includes a first means for generating on the first bidirectional signal path a medium logic level in response to a low level on the receive input on the buffered side, and a second means for generating on the transmit output on the buffered side, a low logic level in response to a low level on the first bidirectional signal path, otherwise generating a high level on the said transmit output, wherein the one or more first stations are adapted to detect the medium and the low levels on the first bidirectional signal path as LOW, and the high logic level on the first bidirectional signal path as HIGH, and wherein further the first means for generating the medium logic level on the first signal path includes an open collector transistor, the emitter of which is connected to VEE, with its collector pulling the first signal path low through a diode connected transistor.

摘要翻译： 一种双向信号传输系统，包括具有适于在所述第一路径上产生逻辑高电平的电路的第一双向信号路径，连接到适于监视所述第一路径上的逻辑电平的第一双向信号路径的一个或多个第一站，以及 在所述第一路径上生成逻辑低电平，接口设备可操作地耦合到第一双向信号路径，所述接口设备具有第一接收输入，其还能够用作能够将第一路径拉低的输出; 以及耦合到所述接口设备的缓冲侧上的发射输出和接收输入的第二双向信号路径，所述接口设备包括第一装置，用于在所述第一双向信号路径上响应于低的信号生成中间逻辑电平 在缓冲侧的接收输入上的电平，以及用于在缓冲侧的发送输出上产生响应于第一双向信号路径上的低电平的低逻辑电平的第二装置，否则在所述第一双向信号路径上产生高电平 发射输出，其中所述一个或多个第一站适于将所述第一双向信号路径上的介质和所述低电平检测为低，并且所述第一双向信号路径上的高逻辑电平为HIGH，并且其中，所述第一装置 在第一信号路径上产生介质逻辑电平包括开路集电极晶体管，其发射极连接到VEE，其集电极拉动第一信号路径低通 一个二极管连接晶体管。

公开(公告)号：US07348803B2

公开(公告)日：2008-03-25

申请号：US11426188

申请日：2006-06-23

申请人： Thi Bui ,  Malcolm Kay ,  David Murfett ,  Mark Potter ,  John Crawford

发明人： Thi Bui ,  Malcolm Kay ,  David Murfett ,  Mark Potter ,  John Crawford

IPC分类号： H03K19/0175

CPC分类号： G06F13/4072

摘要： A bi-directional bus buffer for applications using the I2C and SMBus, or other bus systems operating on similar principles, able to extend the bus load limit by buffering both the SCL and SDA (clock and data) lines, allowing capacitive loads of up to the limit of 400 pF on both sides of the buffer. With the use of an enable function, sections of the bus can be isolated, and then, thorough the use of a number of these buffers, different parts of the system are able to be isolated, and brought on-line successively or in a controlled manner, permitting a controlled start-up, and operation at maximum performance speeds while still having a diverse range of components, operating speeds and loads.

摘要翻译： 用于使用I2C和SMBus或其他以类似原理运行的总线系统的应用的双向总线缓冲器能够通过缓冲SCL和SDA（时钟和数据）线来扩展总线负载限制，允许容量负载达到 缓冲区两边400 pF的极限。 通过使用启用功能，总线的部分可以隔离，然后通过使用多个这些缓冲区，系统的不同部分能够被隔离，并连续上线或被控制 方式，允许控制启动和最大性能运行，同时仍具有不同范围的组件，运行速度和负载。

公开(公告)号：US07315920B2

公开(公告)日：2008-01-01

申请号：US11028293

申请日：2005-01-04

申请人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

发明人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC分类号： G06F12/00

CPC分类号： G06F12/0891

摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.

摘要翻译： 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。 标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。

公开(公告)号：US20060066188A1

公开(公告)日：2006-03-30

申请号：US10952272

申请日：2004-09-28

申请人： John Crawford

发明人： John Crawford

IPC分类号： A47B67/02

CPC分类号： E04B9/003 ,  A47B51/00

摘要： The system includes an enclosure provided upward through a hole provided in a ceiling. The enclosure includes a motor for lifting a set of shelves into the enclosure. The enclosure protects the set of shelves and its contents from moisture and heat, and prevents heat and moisture from escaping from one room to another, across the enclosure. The system is designed to allow installation of the entire system from the lower level, without requiring access to the upper level.

摘要翻译： 该系统包括通过设置在天花板中的孔向上设置的外壳。 外壳包括用于将一组搁架提升到外壳中的电机。 外壳可保护一整套货架及其内容物免受潮湿和热量的影响，并防止热量和湿气从一个房间通过外壳排出。 该系统旨在允许从较低级别安装整个系统，而无需访问上级。

公开(公告)号：US20050120184A1

公开(公告)日：2005-06-02

申请号：US11028293

申请日：2005-01-04

申请人： Nhon Quach ,  John Crawford ,  Greg Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

发明人： Nhon Quach ,  John Crawford ,  Greg Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0891

摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.

摘要翻译： 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。 标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。

公开(公告)号：US20050091480A1

公开(公告)日：2005-04-28

申请号：US10982217

申请日：2004-11-05

申请人： John Crawford ,  Donald Alpert

发明人： John Crawford ,  Donald Alpert

IPC分类号： G06F9/318 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48 ,  G06F7/38 ,  G06F9/00

CPC分类号： G06F9/4812 ,  G06F9/45533

摘要： A computer system is disclosed herein including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing software interrupt (INTn) instructions, using emulation software forming part of the host program in order to emulate the way in which these instructions would have been executed by the earlier microprocessor. As a unique improvement to this overall computer system, certain ones of the INTn instructions are executed by means of emulation software while others are executed by means of the previously written program in cooperation with the given microprocessor and its host operating software program.

摘要翻译： 本文公开了一种计算机系统，其包括专门设计为在虚拟操作模式下操作的给定微处理器，其允许先前为先前设计的单个程序微处理器写入的软件程序在受特定设计的主机之下的受保护的，分页的多任务环境中执行 操作软件程序。 该系统还包括使用形成主机程序的一部分的仿真软件来执行软件中断（INTn）指令的装置，以便模拟这些指令将由较早的微处理器执行的方式。 作为对整个计算机系统的独特改进，INTn指令中的某些指令通过仿真软件执行，而其他指令则通过与给定的微处理器及其主机操作软件程序协作的先前编写的程序来执行。