Control system for self-propelled working vehicle including vehicle
course correction means
    71.
    发明授权
    Control system for self-propelled working vehicle including vehicle course correction means 失效
    自行车工作车辆控制系统,包括车辆校正装​​置

    公开(公告)号:US5079706A

    公开(公告)日:1992-01-07

    申请号:US479189

    申请日:1990-02-13

    IPC分类号: G05D1/00 G05D1/02

    摘要: A steering control system for a self-propelled working vehicle having steerable front and rear wheels. The control system comprises sensors for detecting a directional or orientation error and a sideways error of the vehicle relative to a reference line or lines extending in a vehicle running direction, and a control unit for steering the vehicle in response to signals received from the sensors. The control unit is capable of steering the vehicle in a turn steering mode for turning the front and rear wheels to the same steering angle in opposite directions and a parallel steering mode for turning the front and rear wheels to the same steering angle in the same direction. When the directional error and the sideways error take place simultaneously, the control unit determines directions and angles for turning the front and rear wheels to correct the two errors simultaneously.

    摘要翻译: 一种用于具有可转向的前轮和后轮的自行车作业车辆的转向控制系统。 控制系统包括用于检测车辆相对于在车辆行驶方向上延伸的参考线或线路的方向误差和方向误差和侧向误差的传感器,以及用于响应于从传感器接收的信号而转向车辆的控制单元。 控制单元能够以转向转向模式转向车辆,用于将前轮和后轮转向相反方向的相同转向角,并且还具有用于将前轮和后轮在相同方向上转向相同转向角的平行转向模式 。 当方向误差和侧向误差同时发生时,控制单元确定用于转动前轮和后轮的方向和角度,以同时校正两个误差。

    Bushing in continuous casting dip forming apparatus
    74.
    发明授权
    Bushing in continuous casting dip forming apparatus 失效
    连续铸造浸渍成型设备

    公开(公告)号:US4733716A

    公开(公告)日:1988-03-29

    申请号:US921870

    申请日:1986-10-22

    摘要: There is disclosed a bushing for use in an apparatus for continuously passing a core wire through a crucible holding molten metal to accrete the molten metal on the core wire to form a cast rod. The bushing is connected to the crucible for passing the core wire therethrough into the crucible. The bushing is tubular and has an engaging portion for engaging with the core wire passing therethrough. The engaging portion is made of ceramics material containing a major proportion of at least one selected from the group consisting of zirconia, silicon carbide and silicon nitride.

    摘要翻译: 公开了一种用于连续地将芯线穿过保持熔融金属的坩埚以将芯线上的熔融金属加入以形成浇铸棒的装置的衬套。 衬套连接到坩埚上,以使芯线穿过坩埚。 衬套是管状的并且具有用于与穿过其中的芯线接合的接合部分。 接合部由含有主要比例的选自氧化锆,碳化硅和氮化硅中的至少一种的陶瓷材料制成。

    Process and apparatus for controlling cultivation of microorganisms
    76.
    发明授权
    Process and apparatus for controlling cultivation of microorganisms 失效
    用于控制微生物培养的方法和装置

    公开(公告)号:US4444882A

    公开(公告)日:1984-04-24

    申请号:US324550

    申请日:1981-11-24

    IPC分类号: C12M1/36

    摘要: Cultivation of microorganisms is controlled by measuring a pressure in a cultivation tank, a flow rate of effluent gas from the cultivation tank, and a concentration of carbon dioxide gas in the effluent gas, calculating a partial pressure of carbon dioxide gas in the cultivation tank and an amount of a carbon dioxide gas produced by the microorganisms, calculating an amount of propagated microorganism cells from the resulting partial pressure of carbon dioxide gas and the amount of produced carbon dioxide gas, thereby calculating an amount of microorganism cells in culture liquor, and supplying a substrate in an amount controlled in accordance with the resulting amount of microorganism cells in culture liquor.Microorganisms can be cultivated in high yield and at a high product concentration.

    摘要翻译: 微生物的培养是通过测量培养槽中的压力,来自培养槽的废气流量和排出气体中二氧化碳气体的浓度,计算培养罐中二氧化碳气体的分压和 由微生物产生的二氧化碳气体的量,由二氧化碳气体的分压计算生成的微生物细胞的量和生成的二氧化碳气体的量,计算培养液中的微生物细胞的量, 根据培养液中产生的微生物细胞量控制的量的底物。 微生物可以高产量和高产品浓度培养。

    Time data processing circuit for electronic timepiece
    77.
    发明授权
    Time data processing circuit for electronic timepiece 失效
    电子表的时间数据处理电路

    公开(公告)号:US4253175A

    公开(公告)日:1981-02-24

    申请号:US19572

    申请日:1979-03-12

    CPC分类号: G04G3/025

    摘要: A time data processing circuit for an electronic timepiece comprises a common line; a signal generator for generating time data signal and first, second, third and fourth control signals; first and second shift register circuits; an arithmetic operation circuit for processing the time data signal and the output signal of the first shift register circuit; a first input/output circuit for coupling, in response to the first control signal, the output terminal of the arithmetic operation circuit to the common line and the input terminal of the first shift register circuit and coupling, in response to the second control signal, the common line to the input terminal of the first shift register circuit; and a second input/output circuit for coupling, in response to the third control signal, the output terminal of the second shift register circuit to the input terminal of the second shift register circuit and the common line and coupling, in response to the fourth control signal, the input terminal of the second shift register circuit to the common line.

    摘要翻译: 电子钟表的时间数据处理电路包括公共线; 用于产生时间数据信号和第一,第二,第三和第四控制信号的信号发生器; 第一和第二移位寄存器电路; 用于处理时间数据信号和第一移位寄存器电路的输出信号的算术运算电路; 第一输入/输出电路,用于响应于第一控制信号将算术运算电路的输出端耦合到公共线和第一移位寄存器电路的输入端,并且响应于第二控制信号耦合, 与第一移位寄存器电路的输入端的公共线; 以及第二输入/输出电路,用于响应于所述第三控制信号,将所述第二移位寄存器电路的输出端耦合到所述第二移位寄存器电路的输入端,并且响应于所述第四控制,耦合所述公共线和耦合 信号,第二移位寄存器电路的输入端到公共线。

    Chronograph
    78.
    发明授权
    Chronograph 失效
    计时码表

    公开(公告)号:US4166360A

    公开(公告)日:1979-09-04

    申请号:US862902

    申请日:1977-12-21

    申请人: Tetsuo Yamaguchi

    发明人: Tetsuo Yamaguchi

    CPC分类号: G04F10/04

    摘要: A chronograph includes a reference time counter for measuring a reference time upon receipt of a reference pulse, a plurality of short time counters for measuring a short time difference occurring between runners upon receipt of the reference pulse, a reference pulse control circuit for controlling the supply of the reference pulse to these counters, and an addition circuit for adding the contents of the reference counter to those of the short time counters successively in response to each addition command. The reference pulse control circuit selects either of the reference counter and the short time counters successively in response to each operation of a first switch of a time measuring operator and further supplies the reference pulse to only the selected counter. The reference time counter stores the resultant time resulting from the addition made responsive to each addition command through the operation of a second switch by a single time measuring operator. The resultant time is sequentially displayed through a display circuit so that a single operator can measure the times of a plurality of runners.

    摘要翻译: 计时器包括用于在接收到参考脉冲时测量参考时间的参考时间计数器,用于测量在接收到参考脉冲时在跑步者之间发生的短时差的多个短时间计数器,用于控制供给的参考脉冲控制电路 以及用于响应于每个相加命令,连续地将参考计数器的内容与短时间计数器的内容相加的加法电路。 参考脉冲控制电路响应于时间测量操作员的第一开关的每次操作连续选择参考计数器和短时间计数器中​​的任一个,并且还将所述参考脉冲提供给所选择的计数器。 参考时间计数器通过单个时间测量操作器通过第二开关的操作来存储响应于每个相加命令的相加产生的合成时间。 通过显示电路依次显示合成时间,使得单个操作者可以测量多个跑步者的时间。

    Integrated circuit having one-input terminal with selectively varying
input levels
    80.
    发明授权
    Integrated circuit having one-input terminal with selectively varying input levels 失效
    集成电路具有选择性变化的输入电平的单输入端子

    公开(公告)号:US4115706A

    公开(公告)日:1978-09-19

    申请号:US801911

    申请日:1977-05-31

    申请人: Tetsuo Yamaguchi

    发明人: Tetsuo Yamaguchi

    摘要: An integrated circuit includes an input terminal to which a "1," "float" and "0" level input signals are selectively supplied; a clock pulse generator for generating a second clock pulse during the high level period of a first clock pulse and a third clock pulse during the low level period of the first clock pulse, and first and second latch circuits operated in response to the second and third clock pulses, respectively, of the clock pulse generator. The input terminal is connected through a resistor to the output of the first clock pulse.The input terminal is also connected to the inputs of the first and second latch circuits. The integrated circuit generates three kinds of outputs whose logical states correspond to different levels of three input signals, respectively, which are selectively supplied to said input terminal.

    摘要翻译: 集成电路包括:输入端子,选择性地提供“1”,“浮置”和“0”电平输入信号; 时钟脉冲发生器,用于在第一时钟脉冲的低电平时段期间在第一时钟脉冲和第三时钟脉冲的高电平周期期间产生第二时钟脉冲,以及响应于第二和第三时钟操作的第一和第二锁存电路 分别是时钟脉冲发生器的时钟脉冲。 输入端通过电阻连接到第一个时钟脉冲的输出。