公开(公告)号：US07130226B2

公开(公告)日：2006-10-31

申请号：US11054885

申请日：2005-02-09

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: G11C7/00

CPC classification number: G11C7/1072 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/095 ,  H03L7/0995

Abstract: A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by inverting a signal applied to its input and delaying the signal by a delay that is determined by a delay control signal. A selection circuit couples either the reference clock signal or the delayed clock signal to the input of the voltage controlled delay circuit. When the reference clock signal is coupled to the input of the voltage controlled delay circuit, the clock generating circuit functions as a delay-lock loop. When the delayed clock signal is coupled to the input of the voltage controlled delay circuit, the voltage controlled delay circuit operates as a ring oscillator so that the clock generating circuit functions as a phase-lock loop.

Abstract translation: 时钟发生电路包括相位比较电路，其产生对应于输出时钟信号和参考时钟信号的相对相位的延迟控制信号。 电压控制延迟电路通过反相施加到其输入的信号并延迟由延迟控制信号确定的延迟来产生延迟的时钟信号。 选择电路将参考时钟信号或延迟时钟信号耦合到电压控制延迟电路的输入端。 当参考时钟信号耦合到电压控制延迟电路的输入时，时钟发生电路用作延迟锁定环路。 当延迟时钟信号耦合到电压控制延迟电路的输入端时，电压控制延迟电路作为环形振荡器工作，使得时钟发生电路用作锁相环。

公开(公告)号：US06956418B2

公开(公告)日：2005-10-18

申请号：US10749426

申请日：2003-12-31

Applicant: Jong-Tae Kwak ,  Seong-Hoon Lee

Inventor： Jong-Tae Kwak ,  Seong-Hoon Lee

IPC: H03K5/05 ,  G11C11/407 ,  H03L7/06 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/087

CPC classification number: H03L7/07 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

Abstract: A delay locked loop device includes a first delay line for receiving an external clock signal and a first delay control signal to generate a first internal clock signal; a second delay line for receiving the external clock signal and a second delay control signal or the first delay control signal to generate a second internal clock signal; a first delay control block for receiving the external clock signal to generate the first delay control signal; a second delay control block for receiving the external clock signal to generate the second delay control signal; and a phase detecting block for receiving the first internal clock signal and the second internal clock signal to generate the on-off signal by comparing a phase of the first internal clock signal with a phase of the second internal clock signal.

Abstract translation: 延迟锁定环路装置包括用于接收外部时钟信号的第一延迟线和产生第一内部时钟信号的第一延迟控制信号; 用于接收外部时钟信号的第二延迟线和第二延迟控制信号或第一延迟控制信号以产生第二内部时钟信号; 第一延迟控制块，用于接收外部时钟信号以产生第一延迟控制信号; 第二延迟控制块，用于接收外部时钟信号以产生第二延迟控制信号; 以及相位检测块，用于通过将第一内部时钟信号的相位与第二内部时钟信号的相位进行比较来接收第一内部时钟信号和第二内部时钟信号以产生开关信号。

公开(公告)号：US06914798B2

公开(公告)日：2005-07-05

申请号：US10865860

申请日：2004-06-14

Applicant: Ki-Seop Kwon ,  Seong-Hoon Lee

Inventor： Ki-Seop Kwon ,  Seong-Hoon Lee

IPC: G06F1/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/081 ,  G11C11/22

CPC classification number: H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  H03K5/131 ,  H03K2005/00058 ,  H03K2005/00104 ,  H03L7/0802 ,  H03L7/0814

Abstract: A register controlled delay locked loop (DLL) usable in a semiconductor device is provided. The register controlled delay locked loop includes an internal clock generating unit generating a delayed clock signal and a reference clock signal, a first delay unit compensating for an amount of delay caused by a signal transmission path of the delayed clock signal, a phase comparator detecting a difference between the reference clock signal and the delayed clock signal and thereby generating a detection signal, a controller having a plurality of second delay units for controlling an amount of delay of the delayed clock signal in response to the detection signal, a driver driving a DLL clock signal, and an enable signal generator enabling the driver in response to an activation or non-activation signal of the semiconductor device.

Abstract translation: 提供可用于半导体器件的寄存器控制延迟锁定环（DLL）。 寄存器控制延迟锁定环路包括产生延迟时钟信号和参考时钟信号的内部时钟产生单元，补偿由延迟时钟信号的信号传输路径引起的延迟量的第一延迟单元，相位比较器检测 参考时钟信号和延迟的时钟信号之间的差异，从而产生检测信号;控制器，具有多个第二延迟单元，用于响应于检测信号来控制延迟时钟信号的延迟量;驱动器驱动DLL 时钟信号，以及允许驱动器响应于半导体器件的激活或非激活信号的使能信号发生器。

公开(公告)号：US20050110539A1

公开(公告)日：2005-05-26

申请号：US10722959

申请日：2003-11-26

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03L7/081 ,  H03L7/06

CPC classification number: H03L7/0814

Abstract: Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.

Abstract translation: 微调信号相位调整由多个级联相位混频器提供。 每个相位混合器输出具有其两个输入信号的相位之间的相位的信号。 对于相位混合器的每个后续阶段，相位混合器产生的信号具有较小的相位差，从而提供更好的延迟调整。 可以在数字延迟锁定环路电路中提供多级相位混频器，以提供额外的分层延迟调整。

公开(公告)号：US06768690B2

公开(公告)日：2004-07-27

申请号：US10183666

申请日：2002-06-28

Applicant: Ki-Seop Kwon ,  Seong-Hoon Lee

Inventor： Ki-Seop Kwon ,  Seong-Hoon Lee

IPC: G11C700

CPC classification number: H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  H03K5/131 ,  H03K2005/00058 ,  H03K2005/00104 ,  H03L7/0802 ,  H03L7/0814

Abstract: A resister controlled delay locked loop (DLL) is provided which is capable of reducing current consumption by operating the DLL loop when the semiconductor device is only at an operation mode. A semiconductor device having the register controlled DLL and an internal circuit synchronized with a DLL clock signal output from the register controlled DLL, includes an enable signal generator generating an enable signal for the register controlled DLL to control a generation of the DLL clock signal in response to an activation or non-activation signal of the semiconductor device.

Abstract translation: 提供电阻控制延迟锁定环（DLL），其能够在半导体器件仅处于操作模式时通过操作DLL环路来减少电流消耗。 具有寄存器控制DLL和与从寄存器控制的DLL输出的DLL时钟信号同步的内部电路的半导体器件包括使能信号发生器产生用于寄存器控制的DLL的使能信号，以响应于控制DLL时钟信号的产生 涉及半导体器件的激活或非激活信号。