公开(公告)号：US20070063284A1

公开(公告)日：2007-03-22

申请号：US11492054

申请日：2006-07-25

申请人： Takayuki Kawahara ,  Masanao Yamaoka

发明人： Takayuki Kawahara ,  Masanao Yamaoka

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L29/78645 ,  H01L29/78648

摘要： The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

摘要翻译： 本发明提供一种可在宽温度范围内工作的高速，低功耗的LSI，其具有根据电路的工作特性专门使用具有后栅的MOS晶体管。 在LSI中，使用具有嵌入的氧化膜层的FD-SOI结构，并且将埋入的氧化膜层的下半导体区域用作后栅。 在逻辑电路块中具有小负载的逻辑电路中的后门的电压响应于块外部的激活而被控制。 栅极和背栅彼此连接的晶体管用于产生背栅极驱动信号的电路，以及具有诸如电路块输出部分的重负载的逻辑电路，并且后门直接根据 到门输入信号。

公开(公告)号：US07190609B2

公开(公告)日：2007-03-13

申请号：US10926032

申请日：2004-08-26

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

IPC分类号： G11C11/00

CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is increased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

公开(公告)号：US20060031655A1

公开(公告)日：2006-02-09

申请号：US11242854

申请日：2005-10-05

申请人： Kei Kato ,  Masanao Yamaoka ,  Keiichi Higeta ,  Kazumasa Yanagisawa ,  Shigeru Shimada ,  Kodo Yamauchi ,  Yoshihiro Shinozaki ,  Yasuo Taguchi

发明人： Kei Kato ,  Masanao Yamaoka ,  Keiichi Higeta ,  Kazumasa Yanagisawa ,  Shigeru Shimada ,  Kodo Yamauchi ,  Yoshihiro Shinozaki ,  Yasuo Taguchi

IPC分类号： G06F12/00

CPC分类号： G11C7/106 ,  G06F17/5045 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/104

摘要： The present invention is directed to facilitate change in the specifications of an interface of a memory IP and to improve reusability of the memory IP. A memory module to be mounted on a system LSI or the like is constructed by a basic array and an interface. The basic array is constructed by direct peripheral circuits and a storage circuit. Library data of the basic array is stored in a storage medium such as a CD-R or a magnetic tape and distributed to the user. The library data includes layout pattern data, a logic simulation model defining the operation of the basic array, LSI pattern information such as a layout, device information such as characteristics of a MOS device and layout rules, interface information such as various signal timings, and device specification data such as terminal information.

公开(公告)号：US20050276094A1

公开(公告)日：2005-12-15

申请号：US11151455

申请日：2005-06-14

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Kiyoo Itoh ,  Takayuki Kawahara

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Kiyoo Itoh ,  Takayuki Kawahara

IPC分类号： G11C11/00 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/108

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/108 ,  H01L27/1203 ,  Y10S257/903

摘要： A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.

摘要翻译： SRAM存储器由FD-SOI晶体管组成，通过控制构成驱动晶体管的SOI晶体管的埋入氧化膜下​​的层的电位来提高存储单元的性能。 提高了处于低功率电压状态的SRAM电路的性能。 在由FD-SOI晶体管构成的SRAM存储单元中，控制BOX层下的阱的电位来控制阈值电压Vth，从而增加电流。 因此，可以稳定存储单元的操作。

公开(公告)号：US20050185450A1

公开(公告)日：2005-08-25

申请号：US11048932

申请日：2005-02-03

申请人： Masanori Isoda ,  Masanao Yamaoka

发明人： Masanori Isoda ,  Masanao Yamaoka

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/00 ,  G11C11/412

CPC分类号： G11C5/147 ,  G11C11/412

摘要： Data breakdown due to fluctuation of an operation power source is suppressed by suppressing a sub-threshold leakage current. A semiconductor integrated circuit includes a pair of power source wires, a plurality of static memory cells, a voltage control circuit for controlling an operation voltage applied from the power source wires to the static memory cells, a monitor circuit for monitoring a voltage of the power source wires and a mode control circuit for controlling a plurality of operation modes. The monitor circuit can detect a change of decrease of a potential difference between the pair of power source wires. The voltage control circuit can execute control in such a manner as to reduce the potential difference of a pair of power source nodes of the static memory cell in response to indication of the low power consumption mode by the mode control circuit and can execute control in such a manner as to increase the potential difference of the pair of power source nodes of the static memory cell in response to detection of the decrease of the potential difference between the pair of power source wires by the monitor circuit.

摘要翻译： 通过抑制副阈值泄漏电流来抑制由于操作电源的波动引起的数据故障。 半导体集成电路包括一对电源线，多个静态存储单元，用于控制从电源线施加到静态存储单元的操作电压的电压控制电路，用于监视电源电压的监视电路 源极线和用于控制多个操作模式的模式控制电路。 监视电路可以检测一对电源线之间的电位差的减小的变化。 电压控制电路可以通过模式控制电路响应于低功耗模式的指示来降低静态存储单元的一对电源节点的电位差的方式进行控制，并且可以执行这样的控制 响应于通过监视器电路检测到一对电源线之间的电位差的降低，增加静态存储单元的一对电源节点的电位差的方式。

公开(公告)号：US08633684B2

公开(公告)日：2014-01-21

申请号：US12917523

申请日：2010-11-02

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Minoru Motoyoshi ,  Tetsuya Fukuoka

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Minoru Motoyoshi ,  Tetsuya Fukuoka

IPC分类号： G01R5/14

CPC分类号： G06F1/3203 ,  G06F1/206 ,  H01L21/67276 ,  Y02D10/16

摘要： To provide an LSI having a low power mode that can prevent an apparatus on which the LSI is mounted from resulting in performance degradation, etc. even when its electric power is not reduced in the low power mode. Devised is a circuit that instructs an operation mode and detects whether the LSI operates as specified by the mode, and that measures a current at the time of the low power mode in a pseudo manner and, if despite having shifted to the low power mode, the current is not reduced actually, issues an alarm signal.

摘要翻译： 为了提供具有低功率模式的LSI，即使在低功率模式下其电力没有降低的情况下，也可以防止LSI的装置在其中导致性能劣化等。 设计的是指示操作模式并且检测LSI是否以模式指定的方式操作的电路，并且以伪方式测量低功率模式时的电流，并且如果尽管已经转移到低功率模式， 电流实际上没有减少，发出报警信号。

公开(公告)号：US08451050B2

公开(公告)日：2013-05-28

申请号：US12987112

申请日：2011-01-08

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Minoru Motoyoshi ,  Tetsuya Fukuoka

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Minoru Motoyoshi ,  Tetsuya Fukuoka

IPC分类号： G05F1/10

CPC分类号： G06F1/3203 ,  H03K19/0016

摘要： Information technology equipment includes a circuit block, a local power source line for supplying a power source to the circuit block, a power source line, and a first transistor which is provided with a source-drain path thereof between the power source line and the local power source line, in which the first transistor is controlled to an OFF state in a first state, and is controlled to an ON state in a second state, and when the first state is shifted to the second state, the first transistor is controlled such that a rate of changing a current flowing in the source-drain path of the first transistor does not exceed a predetermined value.

摘要翻译： 信息技术设备包括电路块，用于向电路块提供电源的局部电源线，电源线和在电源线和本地电源线之间设置有源极 - 漏极路径的第一晶体管 电源线，其中第一晶体管在第一状态下被控制为OFF状态，并且在第二状态下被控制为ON状态，并且当第一状态转移到第二状态时，第一晶体管被控制为 改变在第一晶体管的源极 - 漏极路径中流动的电流的速率不超过预定值。

公开(公告)号：US08270230B2

公开(公告)日：2012-09-18

申请号：US13353949

申请日：2012-01-19

申请人： Masanao Yamaoka ,  Kenichi Osada

发明人： Masanao Yamaoka ,  Kenichi Osada

IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C5/14

CPC分类号： G11C8/08 ,  G11C11/412

摘要： The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.

摘要翻译： 半导体器件在用于确定字线激活时间的字线定时信号与参考信号之间进行比较，当比较结果表示读取的低条件时，施加用于放大读取余量的反向栅极偏置 并且当比较结果表示写入余量的低条件时，施加用于扩大写入裕度的反向栅极偏置。 参考信号是根据是否补偿根据字线激活时间（或字线脉冲宽度）而波动的工作裕度，或者根据工艺波动（或阈值电压的变化）来补偿工作裕量波动， 。 通过根据字线脉冲宽度控制背栅极偏压，可以提高根据字线脉冲宽度而波动的工作裕度，以及由于其制造期间的阈值电压的变化而波动的工作裕度。

公开(公告)号：US08264870B2

公开(公告)日：2012-09-11

申请号：US12891208

申请日：2010-09-27

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： G11C11/417 ,  G11C5/14 ,  G11C5/148

摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。

公开(公告)号：US20120217620A1

公开(公告)日：2012-08-30

申请号：US13461848

申请日：2012-05-02

申请人： Makoto SAEN ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

发明人： Makoto SAEN ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.

摘要翻译： 通过采用其中执行一次发送的电路（TR-00T）和用于执行多个接收（TR-10R，TR-20R，TR-30R）的电路的连接拓扑结构来消除对中介操作的需要 连接到一个穿透电极组（例如，TSVGL-0）。 为了实现连接拓扑，即使在堆叠多个LSI的情况下，尤其是用于指定用于发送的各个穿透电极端口或用于接收的可编程存储器元件，以及地址分配 各个贯通电极端口安装在堆叠的LSI中。