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220 条记录 (耗时 0.044 秒)

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    71.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20080116934A1

    公开(公告)日：2008-05-22

    申请号：US11970370

    申请日：2008-01-07

    申请人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Masayuki Miyazaki

    发明人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Masayuki Miyazaki

    IPC分类号： H03K3/01

    CPC分类号： H01L27/0207 ,  H01L27/092 ,  H01L27/105 ,  H03K3/011 ,  H03K3/0315 ,  H03K19/0016

    摘要： A semiconductor device which includes a frequency-variable oscillation circuit including plural inverters, each of which features a PMOS transistor and a NMOS transistor, a first substrate bias generator including a first phase/frequency compare circuit that compares an output signal from the frequency-variable oscillation circuit with a reference clock signal and generating a first substrate bias voltage in response thereto, the first substrate bias voltage being supplied to substrates of the PMOS transistors in the oscillation circuit, and a second substrate bias generator including a second phase/frequency compare circuit that compares the output signal from the frequency-variable oscillation circuit with the reference clock and generating a second substrate bias voltage in response thereto, the second substrate bias voltage being supplied to substrates of the NMOS transistors in the oscillation circuit.

    摘要翻译： 一种半导体器件，包括具有多个反相器的频率可变振荡电路，每个反相器具有PMOS晶体管和NMOS晶体管，第一衬底偏置发生器包括第一相位/频率比较电路，其比较来自频率变量 具有参考时钟信号的振荡电路，并响应于此产生第一衬底偏置电压，第一衬底偏置电压被提供给振荡电路中的PMOS晶体管的衬底，第二衬底偏置发生器包括第二相/频率比较电路 其将来自频率可变振荡电路的输出信号与参考时钟进行比较，并响应于此产生第二衬底偏置电压，第二衬底偏置电压被提供给振荡电路中的NMOS晶体管的衬底。

    Power management for circuits with inactive state data save and restore scan chain
    74.
    发明授权
    Power management for circuits with inactive state data save and restore scan chain 有权
    具有非活动状态数据的电路的电源管理保存并恢复扫描链

    公开(公告)号：US07269780B2

    公开(公告)日：2007-09-11

    申请号：US10674951

    申请日：2003-09-30

    申请人： Yukio Arima ,  Koichiro Ishibashi ,  Takahiro Yamashita

    发明人： Yukio Arima ,  Koichiro Ishibashi ,  Takahiro Yamashita

    IPC分类号： G11C29/00

    CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D10/172

    摘要： An integrated circuit device includes at least one functional module which outputs save data in synchronism with a saving clock signal, a power supply control unit which selects one of the functional modules, and controls stop and resumption of power supply to the selected functional module, a save data storage unit which stores save data output from a functional module selected by the power supply control unit, and an error checking and correction unit which performs error checking and correction for the save data stored in the save data storage unit when the save data is to be restored to the functional module in synchronism with a restoration clock signal.

    摘要翻译： 集成电路装置包括至少一个功能模块，其与保存时钟信号同步地输出保存数据;电源控制单元，选择功能模块之一，并控制对所选择的功能模块的电源的停止和恢复; 保存数据存储单元，其存储从由电源控制单元选择的功能模块输出的保存数据;以及错误检查和校正单元，当保存数据是存储数据时，对存储在保存数据存储单元中的保存数据进行错误校验和校正 与恢复时钟信号同步地恢复到功能模块。

    Semiconductor integrated circuit device
    75.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20070063735A1

    公开(公告)日：2007-03-22

    申请号：US11526612

    申请日：2006-09-26

    申请人： Hiroyuki Mizuno ,  Masataka Minami ,  Koichiro Ishibashi ,  Masayuki Miyazaki

    发明人： Hiroyuki Mizuno ,  Masataka Minami ,  Koichiro Ishibashi ,  Masayuki Miyazaki

    IPC分类号： H03K19/0175

    CPC分类号： H01L27/0207 ,  H01L27/092 ,  H01L27/105 ,  H03K3/011 ,  H03K3/0315 ,  H03K19/0016

    摘要： A semiconductor integrated circuit device which includes a logical circuit containing a MIS transistor on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor in the logical circuit, an oscillation circuit containing a MIS transistor on the semiconductor substrate, and a buffer circuit, the control circuit compares the frequency of the oscillation output and frequency of a clock signal to output a first control signal, the first control signal controls a threshold voltage of the MIS transistor of the oscillation circuit, and the buffer circuit is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor of the logical circuit.

    摘要翻译： 一种半导体集成电路器件，包括在半导体衬底上包含MIS晶体管的逻辑电路，用于控制逻辑电路中的MIS晶体管的阈值电压的控制电路，在半导体衬底上包含MIS晶体管的振荡电路，以及 缓冲电路，控制电路比较振荡输出的频率和时钟信号的频率，输出第一控制信号，第一控制信号控制振荡电路的MIS晶体管的阈值电压，缓冲电路输入 所述第一控制信号输出对应于所述第一控制信号的第二控制信号，所述第二控制信号控制所述逻辑电路的所述MIS晶体管的阈值电压。

    Semiconductor integrated circuit device
    76.
    发明授权
    Semiconductor integrated circuit device 失效

    公开(公告)号：US07112999B2

    公开(公告)日：2006-09-26

    申请号：US11124060

    申请日：2005-05-09

    申请人： Hiroyuki Mizuno ,  Masataka Minami ,  Koichiro Ishibashi ,  Masayuki Miyazaki

    发明人： Hiroyuki Mizuno ,  Masataka Minami ,  Koichiro Ishibashi ,  Masayuki Miyazaki

    IPC分类号： H03K3/01

    CPC分类号： H01L27/0207 ,  H01L27/092 ,  H01L27/105 ,  H03K3/011 ,  H03K3/0315 ,  H03K19/0016

    摘要： A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that the first control signal controls a threshold voltage of the MIS transistor forming the oscillation circuit, and the buffer circuit is constructed so that it is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor forming the logical circuit.

    Semiconductor integrated circuit
    78.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06987415B2

    公开(公告)日：2006-01-17

    申请号：US10765923

    申请日：2004-01-29

    申请人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

    发明人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

    IPC分类号： H03K3/01

    CPC分类号： H01L27/0207 ,  G11C5/14 ,  G11C5/146 ,  G11C5/147 ,  H01L27/0928 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/0016 ,  H01L2924/00

    摘要： In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.

    摘要翻译： 为了提供满足快速操作和低功耗特性的诸如微处理器等的半导体IC单元，保持其高质量，本发明的半导体IC单元被构成为包括主电路（ LOG），其形成在半导体衬底上的晶体管和用于控制施加到衬底的电压的衬底偏置控制电路（VBC），并且主电路包括使用的开关晶体管（MN 1和MP 1） 用于控制施加到衬底的电压，并且从衬底偏置控制电路输出的控制信号被输入到每个开关晶体管的栅极，并且控制信号返回到衬底偏置控制电路。