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公开(公告)号：US6002633A
公开(公告)日：1999-12-14
申请号：US225075
申请日：1999-01-04
CPC分类号： G11C8/12
摘要： A compiler for building at least one compilable SRAM including at least one compilable sub-block. A global control clock generation circuit generates a global control signal. At least one local control logic and speed control circuit controls the at least one compilable sub-block. The local control logic and speed control circuit is controlled by the global control signal. An algorithm receives an input capacity and configuration for the sub-block of the SRAM array. An algorithm determines a number of wordlines and bitlines required to create the sub-block of the input capacity. An algorithm optimizes a cycle time of the sub-block by determining global control clock circuits based upon the number of wordlines and bitlines in the sub-block. An algorithm optimizes access time of the sub-block by determining local speed control circuits based upon the number of wordlines and bitlines.
摘要翻译： 一种用于构建至少一个可编译SRAM（包括至少一个可编译子块）的编译器。 全局控制时钟产生电路产生全局控制信号。 至少一个本地控制逻辑和速度控制电路控制该至少一个可编译子块。 本地控制逻辑和速度控制电路由全局控制信号控制。 算法接收SRAM阵列的子块的输入容量和配置。 算法确定创建输入容量的子块所需的字数和位线数。 算法通过基于子块中的字线和位线的数量确定全局控制时钟电路来优化子块的周期时间。 算法通过基于字线和位线的数量确定本地速度控制电路来优化子块的访问时间。
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72.发明授权Method and built-in self-test apparatus for testing an integrated circuit which capture failure information for a selected failure 失效用于测试集成电路的方法和内置自检装置，其捕获所选故障的故障信息
公开(公告)号：US5912901A
公开(公告)日：1999-06-15
申请号：US823446
申请日：1997-03-24
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319 , G06F11/22 , G11C29/12
CPC分类号： G01R31/318555 , G01R31/2884 , G01R31/319
摘要： A built-in self-test (BIST) apparatus and method for testing an integrated circuit are disclosed which enable capture of failure data for a selected failure. The BIST apparatus comprises a clock generator, which generates at least a first clock signal, and a built-in self-tester, which applies predetermined input data patterns to the integrated circuit in response to the first clock signal. In addition, the BIST apparatus includes a data comparator for comparing output data received from the integrated circuit with expected output data. The data comparator detects a failure within the integrated circuit when the output data received from the integrated circuit differs from the expected output data. The BIST apparatus further includes a clock controller that disables the first clock signal in response to the detection of a selected occurrence of a failure. By enabling testing of the integrated circuit to be halted upon the occurrence of a selected failure, failure analysis of the integrated circuit is enhanced.
摘要翻译： 公开了一种用于测试集成电路的内置自检（BIST）装置和方法，其能够捕获所选故障的故障数据。 BIST装置包括产生至少第一时钟信号的时钟发生器和内置自测试器，其响应于第一时钟信号将预定的输入数据模式应用于集成电路。 此外，BIST装置包括用于将从集成电路接收的输出数据与预期输出数据进行比较的数据比较器。 当从集成电路接收的输出数据与预期输出数据不同时，数据比较器检测集成电路内的故障。 BIST装置还包括时钟控制器，其响应于所选择的故障发生的检测而禁用第一时钟信号。 通过在所选择的故障发生时能够对要停止的集成电路进行测试，增强了集成电路的故障分析。
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公开(公告)号：US08656325B2
公开(公告)日：2014-02-18
申请号：US13348850
申请日：2012-01-12
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/76 , G06F2217/78
摘要： Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.
摘要翻译： 公开了集成电路设计方法，其确定金属部件的最大直流电流，并将其用作设计流程中的设计约束，以避免/最小化电迁移故障。 为了建立设计约束的目的，对短和长金属部件进行不同的处理。 对于短金属部件，确定针对集成电路的给定预期寿命的给定温度的函数的最大直流电，基于Blech长度确定另一最大直流电流，并且选择这两个中的较高者， 用作该短金属部件的设计约束。 对于长金属部件，仅确定作为给定预期寿命的给定温度的函数的最大直流电流作为设计约束。 本文还公开了用于设计集成电路的相关联的系统和程序存储设备实施例。
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公开(公告)号：US08537627B2
公开(公告)日：2013-09-17
申请号：US13223949
申请日：2011-09-01
IPC分类号： G11C7/00
CPC分类号： G11C29/787 , G11C29/4401 , G11C2029/4402
摘要： Used fusebay storage elements are counted so that storage of data may begin at a first unused storage element. Repair register length and a number of previous passes are stored in a fuse header of a fusebay. When a bit of data is sent to the repair register, a repair register position tracker value is changed by one until it reaches a first value. When the first value is reached, a pass tracker value is changed by one. If the first value is not reached, the steps are repeated. A bit counter and/or a page counter may be included.
摘要翻译： 对所使用的熔断器存储元件进行计数，使得数据的存储可以在第一未使用的存储元件开始。 修理寄存器长度和许多以前的通行存储在保险丝盒的保险丝插头中。 当一些数据被发送到修复寄存器时，修复寄存器位置跟踪器值将被改变一到达到第一个值。 当达到第一个值时，通过跟踪器值改变一。 如果没有达到第一个值，则重复这些步骤。 可以包括位计数器和/或页计数器。
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公开(公告)号：US08471595B1
公开(公告)日：2013-06-25
申请号：US13353383
申请日：2012-01-19
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K3/35606 , G06F7/68 , H03K19/1737
摘要： A selectable latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. The output of the parallel pass gates and the additional pass gate is connected to a feedback loop. The feedback loop operates as a dynamic latch for high frequency applications or as a static latch for low frequency applications. Thus, the selectable latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal.
摘要翻译： 可选择的锁存器具有一对并行通过门（接收种子信号的第一并行通道门和接收数据信号的第二并行通道门）。 第一锁存逻辑电路使用由并行通道门输出的信号来执行逻辑运算以产生更新的数据信号。 附加的通过门可操作地连接到第一锁存逻辑电路。 一个附加的传递门控制更新的数据信号的通过。 并联栅极和附加栅极的输出端连接到反馈回路。 反馈回路作为高频应用的动态锁存器或作为低频应用的静态锁存器。 因此，可选择的锁存器包括两个输入到该对并行通道门中，并且仅对接收的数据信号执行四个逻辑运算中的一个。
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公开(公告)号：US08239818B1
公开(公告)日：2012-08-07
申请号：US13080055
申请日：2011-04-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14 , G11C29/12
摘要： A system and associated data structure that can be utilized within a chip design platform to define the structure of an MBIST architecture. A system for generating a memory built in self test (MBIST) design file in described, including a tool for processing an organization file (Org File), wherein the Org File includes lines of code that dictate a structure of the MBIST design file and conform to a data structure defined by the tool; wherein said data structure provides an infrastructure to describe: associations between MBIST components at a design level; associations between MBIST components and hierarchical test ports at the design level; and a serial order of daisy chains among MBIST components within the design level.
摘要翻译： 可以在芯片设计平台内使用的系统和相关数据结构来定义MBIST架构的结构。 一种用于生成内置于自我测试（MBIST）设计文件中的内存的系统，包括用于处理组织文件（Org File）的工具，其中组织文件包括指定MBIST设计文件的结构并符合的代码行 到工具定义的数据结构; 其中所述数据结构提供基础设施以描述：在设计级别的MBIST组件之间的关联; MBIST组件与分级测试端口在设计级别之间的关联; 以及在设计级别的MBIST组件之间的菊花链的串行顺序。
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公开(公告)号：US20120176144A1
公开(公告)日：2012-07-12
申请号：US12986546
申请日：2011-01-07
申请人： Vikram Iyengar , Animesh Khare , Michael R. Ouellette , Narendra K. Rane , Umesh K. Shukla , Pradeep K. Vanama
发明人： Vikram Iyengar , Animesh Khare , Michael R. Ouellette , Narendra K. Rane , Umesh K. Shukla , Pradeep K. Vanama
CPC分类号： G01R31/318572 , G01R31/318541
摘要： A circuit for providing a local scan enable signal includes a first transistor having a first gate coupled to a general scan enable signal, a first source and a first drain and a second transistor having a second gate coupled to a scan clock, a second source coupled to the first drain and a second drain. The circuit also includes a third transistor having a third gate coupled to the general scan enable signal, a third drain coupled to the second drain and a third source and an output stabilizer coupled to the second drain, the output stabilizer including a first inverter and a second inverter coupled together in opposite orientations.
摘要翻译： 用于提供本地扫描使能信号的电路包括具有耦合到一般扫描使能信号的第一栅极的第一晶体管，第一源极和第一漏极以及耦合到扫描时钟的第二栅极的第二晶体管， 到第一排水口和第二排水管。 电路还包括第三晶体管，其具有耦合到通用扫描使能信号的第三栅极，耦合到第二漏极的第三漏极和耦合到第二漏极的第三源极和输出稳定器，输出稳定器包括第一反相器和 第二个逆变器以相反的方向耦合在一起。
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78.发明申请METHOD OF DESIGNING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK 有权设计多状态恢复电路以将状态恢复到功率管理的功能块的方法公开(公告)号：US20090307637A1
公开(公告)日：2009-12-10
申请号：US12135250
申请日：2008-06-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/72
摘要： Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.
摘要翻译： 设计和测试还原逻辑的方法，用于将功能管理逻辑电路的存储元件恢复为值。 在一个实施方式中，所公开的设计方法包括提供逻辑电路的设计，当被实例化时，逻辑电路将具有多个状态，可以在重新启动逻辑电路时将其返回。 由存储元件保存的值被确定并用于将存储元件分类成允许开发还原逻辑的类别，恢复逻辑将恢复适合于特定供电的功率管理逻辑电路的状态。 恢复逻辑设计通过对硬件描述语言进行建模和功耗管理的逻辑电路进行测试，并通过多个测试用例模拟状态数量。 如果设计和测试成功，则可以将恢复逻辑优化为实例化为实际的集成电路。
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公开(公告)号：US20090154269A1
公开(公告)日：2009-06-18
申请号：US11954479
申请日：2007-12-12
CPC分类号： G11C7/20 , G11C5/14 , G11C29/83 , G11C2029/4402
摘要： An approach that manages redundant memory in a voltage island is described. In one embodiment there is a design structure embodied in a machine readable medium used in a design process of a semiconductor device. In this embodiment, the design structure includes one or more voltage islands representing a power cycled region. Each of the one or more voltage islands comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. One or more non-power cycled regions are located about the one or more voltage islands. Each of the one or more non-power cycled regions comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. A redundancy initialization component is coupled to the one or more voltage islands and the one or more non-power cycled regions. The redundancy initialization component is configured to initialize each memory using redundancy and associated repair register with repair data. The redundancy initialization component is configured to initialize a memory using redundancy and associated repair register with repair data independent of, or in conjunction with, the initialization of other memories using redundancy and associated repair registers.
摘要翻译： 描述了管理电压岛中的冗余存储器的方法。 在一个实施例中，存在体现在用于半导体器件的设计过程中的机器可读介质中的设计结构。 在该实施例中，设计结构包括代表功率循环区域的一个或多个电压岛。 一个或多个电压岛中的每一个包括使用冗余的至少一个存储器和使用冗余与每个存储器相关联的修复寄存器。 一个或多个非功率循环区域位于一个或多个电压岛周围。 一个或多个非功率循环区域中的每一个包括使用冗余的至少一个存储器和与使用冗余的每个存储器相关联的修复寄存器。 冗余初始化组件耦合到一个或多个电压岛和一个或多个非功率循环区域。 冗余初始化组件被配置为使用具有修复数据的冗余和相关联的修复寄存器来初始化每个存储器。 冗余初始化组件被配置为使用冗余和相关联的修复寄存器来初始化存储器，其中修复数据与使用冗余和相关联的修复寄存器的其他存储器的初始化无关或与其一起使用。
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80.发明申请Programmable Locking Mechanism For Secure Applications In An Integrated Circuit 审中-公开可编程锁定机制，用于集成电路中的安全应用公开(公告)号：US20080155151A1
公开(公告)日：2008-06-26
申请号：US11615137
申请日：2006-12-22
IPC分类号： G06F21/00
CPC分类号： G06K19/073 , G06K19/07309
摘要： A programmable locking mechanism for use in an integrated circuit is disclosed. In particular, the programmable locking mechanism may include an access code storage circuit for storing a security access code and a code input register whose outputs feed a comparator circuit that generates a locking signal. The state of the locking signal depends on whether the contents of the access code storage circuit and the code input register match. Additionally, a blocking circuit is provided that interrupts a programming input to the access code storage circuit and, thus, allows or denies access via the programming input to the access code storage circuit depending on the state of the locking signal. Additionally, the locking signal is distributed to sensitive logic circuits within the integrated circuit for preventing and/or allowing (depending on state) access thereto.
摘要翻译： 公开了一种用于集成电路的可编程锁定机构。 特别地，可编程锁定机构可以包括用于存储安全访问代码的访问代码存储电路和其输出馈送产生锁定信号的比较器电路的代码输入寄存器。 锁定信号的状态取决于访问代码存储电路和代码输入寄存器的内容是否匹配。 此外，提供一种阻塞电路，其中断对访问代码存储电路的编程输入，并且因此根据锁定信号的状态允许或拒绝通过对访问代码存储电路的编程输入的访问。 此外，锁定信号被分配到集成电路内的敏感逻辑电路，用于防止和/或允许（取决于状态）对其的访问。
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