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    System, Device and Methods of Manufacture
    74.
    发明申请
    System, Device and Methods of Manufacture 有权

    公开(公告)号：US20220367267A1

    公开(公告)日：2022-11-17

    申请号：US17870075

    申请日：2022-07-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Wei Ling Chang ,  Chuei-Tang Wang ,  Tin-Hao Kuo ,  Che-Wei Hsu

    IPC: H01L21/768 ,  H01L23/00 ,  H01L21/77 ,  H01L23/528 ,  H01L25/18

    Abstract: Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.

    Package structure and manufacturing method thereof
    75.
    发明授权
    Package structure and manufacturing method thereof 有权

    公开(公告)号：US11495573B2

    公开(公告)日：2022-11-08

    申请号：US16805838

    申请日：2020-03-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

    IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13

    Abstract: A package structure includes a first semiconductor die, a second semiconductor die, a redistribution circuit structure, and a semiconductor device. The redistribution circuit structure has a first surface and a second surface opposite to the first surface, where the first surface is in contact with the first semiconductor die and the second semiconductor die, and the redistribution circuit structure is disposed on and electrically connected to the first semiconductor die and the second semiconductor die. The redistribution circuit structure includes a recess extending from the second surface toward the first surface. The semiconductor device is located in the recess and electrically connected to the first semiconductor die and the second semiconductor die through the redistribution circuit structure.

    Integrated Circuit Package and Method
    76.
    发明申请
    Integrated Circuit Package and Method 有权

    公开(公告)号：US20220262783A1

    公开(公告)日：2022-08-18

    申请号：US17175081

    申请日：2021-02-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang

    IPC: H01L25/00 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31

    Abstract: In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.

    Deep Partition Power Delivery with Deep Trench Capacitor
    77.
    发明申请
    Deep Partition Power Delivery with Deep Trench Capacitor 有权

    公开(公告)号：US20220262778A1

    公开(公告)日：2022-08-18

    申请号：US17232325

    申请日：2021-04-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chieh-Yen Chen

    IPC: H01L25/16 ,  H01L23/00 ,  H01L23/48 ,  H01L21/304 ,  H01L21/683 ,  H01L21/768

    Abstract: A method includes bonding a capacitor die to a device die. The device die includes a first semiconductor substrate, active devices at a surface of the first semiconductor substrate, a plurality of low-k dielectric layers, a first dielectric layer over and contacting a top low-k dielectric layer in the plurality of low-k dielectric layers, and a first plurality of bond pads in the first dielectric layer. The capacitor die includes a second dielectric layer bonding to the first dielectric layer, a second plurality of bond pads in the second dielectric layer and bonding to the first plurality of bond pads, and a capacitor electrically coupled to the second plurality of bond pads. After the capacitor die is bonded to the device die, an aluminum-containing pad is formed over the capacitor die and electrically coupled to the device die. A polymer layer is formed over the aluminum-containing pad.

    Integrated circuit package and method
    78.
    发明授权
    Integrated circuit package and method 有权

    公开(公告)号：US11387222B2

    公开(公告)日：2022-07-12

    申请号：US16882054

    申请日：2020-05-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Wei Ling Chang ,  Chuei-Tang Wang ,  Chieh-Yen Chen

    IPC: H01L25/16 ,  H01L23/00

    Abstract: In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

    Die stacks and methods forming same
    79.
    发明授权
    Die stacks and methods forming same 有权

    公开(公告)号：US11380655B2

    公开(公告)日：2022-07-05

    申请号：US17080130

    申请日：2020-10-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang

    IPC: H01L23/522 ,  H01L25/065 ,  H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48

    Abstract: A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die.

    Package structure and package-on-package structure
    80.
    发明授权
    Package structure and package-on-package structure 有权

    公开(公告)号：US11239157B2

    公开(公告)日：2022-02-01

    申请号：US16995779

    申请日：2020-08-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Wei-Ting Chen

    IPC: H01L23/522 ,  H01L23/00 ,  H01L49/02 ,  H01L21/768 ,  H01L23/532 ,  H01L21/56

    Abstract: A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.

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