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    Methods of Forming Contact Features in Field-Effect Transistors
    71.
    发明申请
    Methods of Forming Contact Features in Field-Effect Transistors 有权

    公开(公告)号：US20210384352A1

    公开(公告)日：2021-12-09

    申请号：US17412032

    申请日：2021-08-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Zhen Yu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/78 ,  H01L21/02 ,  H01L27/088 ,  H01L29/66

    Abstract: A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.

    METHOD FOR FORMING LONG CHANNEL BACK-SIDE POWER RAIL DEVICE
    74.
    发明申请
    METHOD FOR FORMING LONG CHANNEL BACK-SIDE POWER RAIL DEVICE 有权

    公开(公告)号：US20210351079A1

    公开(公告)日：2021-11-11

    申请号：US17068037

    申请日：2020-10-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Zhi-Chang Lin ,  Li-Zhen Yu

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78

    Abstract: A method of forming a semiconductor transistor device. The method comprises forming a fin-shaped channel structure over a substrate and forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite endings of the fin structure. The method further comprises forming a metal gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain epitaxial structure and the second source/drain epitaxial structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

    Selective Liner on Backside Via and Method Thereof
    75.
    发明申请
    Selective Liner on Backside Via and Method Thereof 有权

    公开(公告)号：US20210336004A1

    公开(公告)日：2021-10-28

    申请号：US16944263

    申请日：2020-07-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

    IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

    Abstract: A method includes providing a structure having a substrate, a fin, source/drain (S/D) features, an isolation structure adjacent to sidewalls of the fin, one or more channel layers over a first dielectric layer and connecting the S/D features, and a gate structure engaging the one or more channel layers. The method further includes thinning down the structure from its backside until the fin is exposed and selectively etching the fin to form a trench that exposes surfaces of the S/D features, the first dielectric layer, and the isolation structure. The method further includes forming a silicide feature on the S/D features and depositing an inhibitor on the silicide feature but not on the surface of the first dielectric layer and the isolation structure, depositing a dielectric liner layer on the surfaces of the isolation structure and the first dielectric layer but not on the inhibitor, and selectively removing the inhibitor.

    Semiconductor device and method of forming same
    76.
    发明授权
    Semiconductor device and method of forming same 有权

    公开(公告)号：US11145728B2

    公开(公告)日：2021-10-12

    申请号：US16809876

    申请日：2020-03-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/311

    Abstract: A method includes forming a gate structure over a fin protruding above a substrate, forming a gate spacer layer on sidewalls of the gate structure, forming an etch stop layer on sidewalls of the gate spacer layer, replacing the gate structure with a gate stack, forming a source/drain contact adjacent the etch stop layer, recessing the gate stack to form a first recess, filling the first recess with a first dielectric material, recessing the source/drain contact and the etch stop layer to form a second recess, filling the second recess with a second dielectric material, recessing the second dielectric material and the gate spacer layer to form a third recess, and filling the third recess with a third dielectric material, wherein the composition of the third dielectric material is different from that of the first dielectric material and the second dielectric material.

    USING A LINER LAYER TO ENLARGE PROCESS WINDOW FOR A CONTACT VIA
    77.
    发明申请
    USING A LINER LAYER TO ENLARGE PROCESS WINDOW FOR A CONTACT VIA 有权

    公开(公告)号：US20210280454A1

    公开(公告)日：2021-09-09

    申请号：US16808902

    申请日：2020-03-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Zhen Yu ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Yu-Ming Lin ,  Lin-Yu Huang

    IPC: H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/66

    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure.

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME
    78.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME 有权

    公开(公告)号：US20210134969A1

    公开(公告)日：2021-05-06

    申请号：US16809876

    申请日：2020-03-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L29/66

    Abstract: A method includes forming a gate structure over a fin protruding above a substrate, forming a gate spacer layer on sidewalls of the gate structure, forming an etch stop layer on sidewalls of the gate spacer layer, replacing the gate structure with a gate stack, forming a source/drain contact adjacent the etch stop layer, recessing the gate stack to form a first recess, filling the first recess with a first dielectric material, recessing the source/drain contact and the etch stop layer to form a second recess, filling the second recess with a second dielectric material, recessing the second dielectric material and the gate spacer layer to form a third recess, and filling the third recess with a third dielectric material, wherein the composition of the third dielectric material is different from that of the first dielectric material and the second dielectric material.

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