公开(公告)号：US11011625B2

公开(公告)日：2021-05-18

申请号：US16510554

申请日：2019-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Yu-Ming Lin ,  Chung-Wei Hsu

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

公开(公告)号：US20200098622A1

公开(公告)日：2020-03-26

申请号：US16510554

申请日：2019-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Yu-Ming Lin ,  Chung-Wei Hsu

IPC: H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

公开(公告)号：US20200006531A1

公开(公告)日：2020-01-02

申请号：US16544196

申请日：2019-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu ,  Huan-Chieh Su ,  Ting-Hung Hsu ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/768

Abstract: A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.

公开(公告)号：US10388771B1

公开(公告)日：2019-08-20

申请号：US16021344

申请日：2018-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu ,  Huan-Chieh Su ,  Ting-Hung Hsu ,  Chih-Hao Wang

IPC: H01L21/311 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768

Abstract: A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.

公开(公告)号：US12283521B2

公开(公告)日：2025-04-22

申请号：US18420209

申请日：2024-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

公开(公告)号：US12266658B2

公开(公告)日：2025-04-01

申请号：US18356677

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes an isolation structure, a source/drain region over the isolation structure, a gate structure over the isolation structure and adjacent to the source/drain region, an interconnect layer over the source/drain region and the gate structure, an isolating layer below the gate structure, and a contact structure under the source/drain region. The contact structure has a first portion and a second portion. The first portion is below the second portion. The second portion extends through the isolating layer and protrudes above the isolating layer. A portion of the isolating layer is vertically between the gate structure and the first portion of the contact structure.

公开(公告)号：US12266654B2

公开(公告)日：2025-04-01

申请号：US16215676

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Mao-Lin Huang ,  Zhi-Chang Lin

IPC: H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.

公开(公告)号：US12243823B2

公开(公告)日：2025-03-04

申请号：US17476962

申请日：2021-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/535 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.

公开(公告)号：US20240387664A1

公开(公告)日：2024-11-21

申请号：US18788305

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Huan-Chieh Su

IPC: H01L29/417 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

Abstract: A device includes a device layer including a first transistor, a first interconnect structure on a front-side of the device layer, and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric material on the backside of the device layer, a contact extending through the first dielectric material to a first source/drain region of the first transistor, and a first conductive layer including a first conductive line electrically connected to the first source/drain region through the contact.

公开(公告)号：US12132092B2

公开(公告)日：2024-10-29

申请号：US17743992

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/4238 ,  H01L21/76804 ,  H01L21/823418 ,  H01L29/0665 ,  H01L29/4933 ,  H01L29/6656

Abstract: Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a second transistor structure adjacent the first transistor structure; a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a second dielectric layer on the backside of the second transistor structure; a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact.