摘要:
The present invention has been conceived in view of the above described situation, and an object of the invention is to provide an information processing device, data transfer method and information storage medium that can commence data transfer to an I/O device immediately, and can stably exhibit data transfer performance. In an information processing device provided with hardware for sharing an address translation table, for translating logical addresses of a memory to physical addresses, between a main processor and a sub-processor, one of the sub-processors is caused to function as means for receiving a transfer request designating a logical address of the memory, means for translating the logical address that has been designated in the transfer request to a physical address using the shared address translation table, and means for executing transfer processing for data stored in the memory 14 according to the translated physical address.
摘要:
This brushless motor includes: stators respectively having wires and cores around which the wires are respectively wound; a housing which houses the stators; a rotor rotatably attached to the housing; and a bracket having conductive bodies to which terminal leading lines of the wires are respectively connected and an insulating body supporting the conductive bodies, and installed in an opening of the housing; wherein the conductive bodies are insert-molded to the insulating body.
摘要:
A DMA controller (DMAC) for handling a list DMA command in a computer system is provided. The computer system has at least one processor and a system memory, the list DMA command relates to an effective address (EA) of the system memory, and the at least one processor has a local storage. The DMAC includes a DMA command queue (DMAQ) coupled to the local storage and configured to receive the list DMA command from the local storage and to enqueue the list DMA command. An issue logic is coupled to the DMAQ and configured to issue an issue request to the DMAQ. A request interface logic (RIL) is coupled to the DMAQ and configured to read the list DMA command based on the issue request. The RIL is further coupled to the local storage and configured to send a fetch request to the local storage to initiate a fetch of a list element of the list DMA command from the local storage to the DMAQ. Each list element comprises a stall bit indicating whether the list element is fenced and a DMA completion logic (DCL) is coupled to the at least one processor, the issue logic, and the RIL, and configured to indicate completion of all outstanding bus requests relating to the list element.
摘要:
A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.
摘要:
A shock absorbing structure of a two-wheeled vehicle capable of sufficiently absorbing shock and desirably maintain the steerability of the two-wheeled vehicle. The structure includes a shock absorbing member projecting from a front wheel, wherein the shock absorbing member is crashed when the vehicle collides with an obstacle so as to absorb shock. A ceiling wall of the shock absorbing member is located at such a position that the ceiling wall does not block a forward viewing area for a driver. A center of a leading end contact surface of the shock absorbing member is located at a position higher than a vertical position of a center of gravity G of both a motorcycle and the driver, and right and left side surfaces of the shock absorbing member are offset to a center of a vehicular body from right and left side surfaces of the motorcycle.
摘要:
Methods and apparatus provide for transferring blocks of data between a shared memory and one or more of a plurality of parallel processors, each processor including a local memory; executing one or more programs within the local memory of one or more of the processors, wherein the one or more programs are coded such that they do not rely on data caching within the processor; and buffering not more than about three instructions from any local memory in any instruction buffer of any processor, wherein the instruction buffer of each processor is adapted to process instructions with substantially maximal efficiency when the one or more programs are coded such that they do not rely on data caching within the processor.
摘要:
Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being operatively coupled to a first of a plurality of parallel processors capable of operative communication with a shared memory; facilitating the data transfer into the local memory; and producing a synchronization signal indicating that the data transfer into the local memory has been completed.
摘要:
To provide an air bag apparatus for a small size vehicle, wherein a seat for a driver is provided at a rear portion of a vehicle body and an instrument panel, which a driver on the seat can visually observe is provided at a front portion of the vehicle body. The air bag apparatus assures a wide range of inflation and expansion of an air bag and can be applied to a conventional small size vehicle without a significant design change. A plurality of air bags which can constrain a driver on a seat from a forward direction are connected to each other by a connection mechanism and are accommodated in a folded state in an instrument panel.
摘要:
Methods and systems are disclosed for staggered address mapping of memory regions in shared memory for use in multi-threaded processing of single instruction multiple data (SIMD) threads and multi-scalar threads without inter-thread memory region conflicts and permitting transition from SIMD mode to multi-scalar mode without the need for rearrangement of data stored in the memory regions.
摘要:
A processor is provided which has a modular organization including at least one local store operable to store data and instructions for execution, at least one functional unit operable to execute instructions on data provided from the local store, and at least one issue logic unit operable to convert instructions provided from the local store into operations of the functional unit for executing the instructions. Each such issue logic unit is operable to control execution of the instruction by one or more functional units according to a common instruction set. When the processor includes a plurality of functional units, the at least one issue logic unit is operable to decode a unitary instruction provided from the local store to simultaneously operate all of the functional units according to the unitary instruction. Each issue logic unit is further operable to decode multiple instructions to separately operate first and second subsets of the plurality of functional units, wherein each subset is operated according to a respective one of the multiple instructions.