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    Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment
    1.
    发明授权
    Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment 有权
    非对称异构多处理器环境中的内存障碍原语

    公开(公告)号：US07725618B2

    公开(公告)日：2010-05-25

    申请号：US10902474

    申请日：2004-07-29

    申请人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

    发明人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

    摘要翻译： 本发明提供了一种用于在直接存储器访问（DMA）设备中创建存储障碍的方法和装置。 接收到存储器屏障命令并接收存储器命令。 内存命令是根据内存屏障命令执行的。 基于内存障碍命令启动总线操作。 基于总线操作接收总线操作确认。 基于总线操作确认执行存储器障碍命令。 在特定方面，存储器屏障命令是直接存储器访问同步（dmasync），并且直接存储器访问强制执行输入/输出（dmaeie））命令的按顺序执行。

    Establishing command order in an out of order DMA command queue
    2.
    发明授权
    Establishing command order in an out of order DMA command queue 失效
    在命令行DMA命令队列中建立命令顺序

    公开(公告)号：US07243200B2

    公开(公告)日：2007-07-10

    申请号：US10891772

    申请日：2004-07-15

    申请人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

    发明人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

    IPC分类号： G06F12/00

    CPC分类号： G06F13/28

    摘要： A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.

    摘要翻译： 提供了一种用于控制存储器访问的方法，装置和计算机程序。 直接存储器访问（DMA）单元已经在许多总线架构中变得普遍。 然而，管理有限的系统资源已成为多个DMA单元的挑战。 为了管理生成的多个命令并保留依赖关系，使用命令中的嵌入式标志或障碍命令。 这些操作然后可以控制执行命令的顺序，以便保留依赖性。

    System and method for identifying and accessing streaming data in a locked portion of a cache
    4.
    发明授权
    System and method for identifying and accessing streaming data in a locked portion of a cache 失效
    用于在高速缓存的锁定部分中识别和访问流数据的系统和方法

    公开(公告)号：US06961820B2

    公开(公告)日：2005-11-01

    申请号：US10366440

    申请日：2003-02-12

    申请人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David J. Shippy ,  Thuong Quang Truong

    发明人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David J. Shippy ,  Thuong Quang Truong

    IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/12

    CPC分类号： G06F12/126

    摘要： A system and method are provided for efficiently processing data with a cache in a computer system. The computer system has a processor, a cache and a system memory. The processor issues a data request for streaming data. The streaming data has one or more small data portions. The system memory is in communication with the processor. The system memory has a specific area for storing the streaming data. The cache is coupled to the processor. The cache has a predefined area locked for the streaming data. A cache controller is coupled to the cache and is in communication with both the processor and the system memory to transmit at least one small data portion of the streaming data from the specific area of the system memory to the predefined area of the cache when the one small data portion is not found in the predefined area of the cache.

    摘要翻译： 提供了一种系统和方法，用于在计算机系统中用高速缓存高效地处理数据。 计算机系统具有处理器，缓存和系统存储器。 处理器发出流数据的数据请求。 流数据具有一个或多个小数据部分。 系统存储器与处理器通信。 系统存储器具有用于存储流数据的特定区域。 缓存耦合到处理器。 高速缓存具有为流数据锁定的预定义区域。 高速缓存控制器耦合到高速缓存，并且与处理器和系统存储器通信，以将流式数据的至少一个小数据部分从系统存储器的特定区域发送到高速缓存的预定义区域 在缓存的预定义区域中没有找到小数据部分。

    On-chip data transfer in multi-processor system
    5.
    发明授权
    On-chip data transfer in multi-processor system 失效
    多处理器系统中的片上数据传输

    公开(公告)号：US06820143B2

    公开(公告)日：2004-11-16

    申请号：US10322127

    申请日：2002-12-17

    申请人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David Shippy ,  Thuong Quang Truong

    发明人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David Shippy ,  Thuong Quang Truong

    IPC分类号： G06F1328

    CPC分类号： G06F12/0817 ,  G06F12/0897

    摘要： A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.

    摘要翻译： 提供了一种通过在不同处理器之间提供直接数据传输来提高计算机系统的性能的系统和方法。 该系统包括第一和第二处理器。 第一个处理器需要数据。 该系统还包括与第一处理器通信的目录。 目录接收到数据的数据请求，并包含有关数据存储位置的信息。 缓存耦合到第二处理器。 当发现数据被存储在高速缓存中时，内部总线耦合在第一处理器和高速缓存之间以将数据从高速缓存传送到第一处理器。

    Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation
    7.
    发明授权
    Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation 失效
    具有用于计算应用的带宽管理的微处理器和管理带宽分配的相关方法

    公开(公告)号：US07107363B2

    公开(公告)日：2006-09-12

    申请号：US10464882

    申请日：2003-06-19

    申请人： Jeffrey Douglas Brown ,  Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Takeshi Yamazaki

    发明人： Jeffrey Douglas Brown ,  Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Takeshi Yamazaki

    IPC分类号： G06F3/00

    CPC分类号： G06F9/5011 ,  G06F2209/5014

    摘要： The present invention discloses, in one aspect, a microprocessor. In one embodiment, the microprocessor includes a processing element configured to process an application using a bandwidth. The microprocessor also includes an access shaper coupled to the processing element and configured to shape storage requests for the processing of the application. In this embodiment, the microprocessor further includes bandwidth management circuitry coupled to the access shaper and configured to track the bandwidth usage based on the requests. A method of coordinating bandwidth allocation and a processor assembly are also disclosed.

    摘要翻译： 本发明在一个方面公开了一种微处理器。 在一个实施例中，微处理器包括被配置为使用带宽来处理应用的处理元件。 微处理器还包括一个接入整形器，它与处理元件相耦合，并配置成形成用于处理应用的存储请求。 在该实施例中，微处理器还包括耦合到接入整形器的带宽管理电路，并且被配置为基于请求跟踪带宽使用。 还公开了一种协调带宽分配的方法和处理器组件。

    System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups
    9.
    发明授权
    System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups 失效
    用于异步DMA命令完成通知的系统，其中包括标签的DMA命令属于多个标签组

    公开(公告)号：US07546393B2

    公开(公告)日：2009-06-09

    申请号：US11695436

    申请日：2007-04-02

    申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  Peichum Peter Liu ,  Thuong Quang Truong ,  Takeshi Yamazaki

    发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  Peichum Peter Liu ,  Thuong Quang Truong ,  Takeshi Yamazaki

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.

    摘要翻译： 本发明提供一种包括配置成接收包括标签的DMA命令的DMA队列的系统，其中标签属于多个标签组之一。 计数器耦合到DMA队列，并配置为在DMA队列接收到DMA命令时增加标签组所属标签组的标签组计数，并在执行DMA命令时递减标签组计数。 标签组计数状态寄存器耦合到计数器，并被配置为存储多个标签组中的每一个的标签组计数。 并且标签组计数状态寄存器被进一步配置为接收对标签组状态的请求并响应对标签组状态的请求。

    Method for processor to use locking cache as part of system memory
    10.
    发明授权
    Method for processor to use locking cache as part of system memory 失效
    处理器使用锁定缓存作为系统内存的一部分的方法

    公开(公告)号：US07290106B2

    公开(公告)日：2007-10-30

    申请号：US10976260

    申请日：2004-10-28

    申请人： Michael Norman Day ,  Charles Johns ,  Thuong Truong

    发明人： Michael Norman Day ,  Charles Johns ,  Thuong Truong

    IPC分类号： G06F12/00

    CPC分类号： G06F12/126 ,  G06F12/0848 ,  G06F2212/2515

    摘要： The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. The locking cache or other fast memory can be used as additional system memory. In an embodiment of the invention, the locking cache is one or more sets of ways, but not all of the sets or ways, of a multiple set associative cache.

    摘要翻译： 本发明提供了一种用于处理器将数据写入高速缓存或其他快速存储器的方法，而不将其写入主存储器。 此外，数据被“锁定”到高速缓存或其他快速存储器中，直到它被加载使用为止。 数据保留在锁定缓存中，直到它在软件控制下被特别覆盖为止。 锁定缓存或其他快速存储器可用作附加系统内存。 在本发明的实施例中，锁定高速缓存是多组关联高速缓存的一组或多组方式，但不是所有的集合或方式。