公开(公告)号：US20230134131A1

公开(公告)日：2023-05-04

申请号：US17512908

申请日：2021-10-28

Applicant: Texas Instruments Incorporated

Inventor： Pushpa Mahalingam ,  Alexei Sadovnikov

IPC: H01L27/092 ,  H01L21/8238

Abstract: A microelectronic device including an analog MOS transistor. The analog transistor has a body well having a first conductivity type in a semiconductor material of a substrate of the microelectronic device. The body well extends deeper in the substrate than a field relief dielectric layer at the top surface of the semiconductor material. The analog transistor has a drain well and a source well having a second, opposite, conductivity type in the semiconductor material, both contacting the body well. The drain well and the source well extend deeper in the substrate than the field relief dielectric layer. The analog transistor has a gate on a gate dielectric layer over the body well. The drain well and the source well extend partway under the gate at the top surface of the semiconductor material.

公开(公告)号：US11527617B2

公开(公告)日：2022-12-13

申请号：US17201021

申请日：2021-03-15

Applicant: Texas Instruments Incorporated

Inventor： Sheldon Douglas Haynie ,  Alexei Sadovnikov

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.

公开(公告)号：US11469315B2

公开(公告)日：2022-10-11

申请号：US17017341

申请日：2020-09-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Natalia Lavrovskaya ,  Guruvayurappan Mathur

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/423

Abstract: In a described example, a bipolar junction transistor includes a substrate. An emitter region, a base region, and a collector region are each formed in the substrate. A gate-type structure is formed on the substrate between the base region and the emitter region. A contact is coupled to the gate-type structure, and the contact is adapted to be coupled to a source of DC voltage.

公开(公告)号：US20220208973A1

公开(公告)日：2022-06-30

申请号：US17156612

申请日：2021-01-24

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Alexei Sadovnikov ,  Henry Litzmann Edwards ,  Jarvis Benjamin Jacobs

IPC: H01L29/26 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

Abstract: A semiconductor device including drain extended metal oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region each having a first dopant type spaced apart along a surface of a semiconductor material having a second opposite conductivity type. A gate electrode over the semiconductor material surface between the source region and the drain region. A diffusion suppression implant region in the semiconductor material extends from the source region under the gate electrode. The diffusion suppression implant region includes a body region having the second opposite conductivity type and comprises at least one of carbon, nitrogen, and fluorine.

公开(公告)号：US20220068649A1

公开(公告)日：2022-03-03

申请号：US17411431

申请日：2021-08-25

Applicant: Texas Instruments Incorporated

Inventor： Mona M. Eissa ,  Jason R. Heine ,  Pushpa Mahalingam ,  Henry Litzmann Edwards ,  James Robert Todd ,  Alexei Sadovnikov

IPC: H01L21/266 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

Abstract: A method of fabricating an IC includes providing a substrate including a semiconductor surface having well diffusions for a plurality of devices including bipolar, complementary metal oxide semiconductor (CMOS), and double-diffused MOS (DMOS) devices. A polysilicon layer is deposited on a dielectric layer over the semiconductor surface, an anti-reflective coating (ARC) layer is formed on the polysilicon layer, and a photoresist pattern is formed on the ARC layer. The ARC layer is etched in areas exposed by the photoresist pattern to define areas including gate areas having the ARC layer on the polysilicon layer. The photoresist pattern is removed. Polysilicon etching is performed in areas lacking the ARC layer to form polysilicon gates having a remaining ARC portion of the ARC layer thereon. A self-aligned ion implant uses the remaining ARC portion as an additional implant blocking layer for the polysilicon gates, and the remaining ARC portion is stripped.

公开(公告)号：US20220037468A1

公开(公告)日：2022-02-03

申请号：US17201021

申请日：2021-03-15

Applicant: Texas Instruments Incorporated

Inventor： Sheldon Douglas Haynie ,  Alexei Sadovnikov

IPC: H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.

公开(公告)号：US11217665B2

公开(公告)日：2022-01-04

申请号：US16781674

申请日：2020-02-04

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Natalia Lavrovskaya

IPC: H01L29/08 ,  H01L21/82 ,  H01L29/732 ,  H01L29/10 ,  H01L29/66 ,  H01L27/06 ,  H01L21/8249 ,  H01L21/265 ,  H01L21/266 ,  H01L29/36

Abstract: A semiconductor device includes a bipolar junction transistor having a collector, a base, and an emitter. The collector includes a current collection region, a constriction region laterally adjacent to the current collection region, and a contact region laterally adjacent to the constriction region, located opposite from the current collection region. The current collection region, the constriction region laterally, and the contact region all have the same conductivity type. The base includes a current transmission region contacting the current collection region and a constricting well laterally adjacent to, and contacting, the current transmission region and contacting the constriction region. The current transmission region and the constricting well have an opposite conductivity type than the current collection region, the constriction region laterally, and the contact region.

公开(公告)号：US11152505B2

公开(公告)日：2021-10-19

申请号：US16021601

申请日：2018-06-28

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Andrew Derek Strachan ,  Henry Litzmann Edwards ,  Dhanoop Varghese ,  Xiaoju Wu ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265 ,  H01L29/08 ,  H01L21/266

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.

公开(公告)号：US20210280714A1

公开(公告)日：2021-09-09

申请号：US17330095

申请日：2021-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Natalia Lavrovskaya

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L29/06

Abstract: An integrated circuit chip and a method of fabricating the IC chip to include a transistor having a thick gate oxide in combination with STI. The method provides a wafer for which a source region location, a drain contact region location, an extended drain region location and a gate region location have been defined and forms an STI structure overlying the extended drain region location. After growing a gate oxide layer over the gate region location and a portion of the extended drain region location, the method forms a gate structure on the gate oxide layer, the gate structure having a gap overlying the intersection of an edge of the STI structure with the gate oxide layer.

公开(公告)号：US11081558B2

公开(公告)日：2021-08-03

申请号：US16812311

申请日：2020-03-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Umamaheswari Aghoram ,  Pushpa Mahalingam ,  Alexei Sadovnikov ,  Eugene C Davis

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/221 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/761 ,  H01L29/10

Abstract: A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure located between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon oxide.