利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

147 条记录 (耗时 0.038 秒)

    STACKED DIE MEMORY
    72.
    发明申请
    STACKED DIE MEMORY 审中-公开
    堆叠式电池存储器

    公开(公告)号：US20090196093A1

    公开(公告)日：2009-08-06

    申请号：US12023630

    申请日：2008-01-31

    申请人： Thomas Happ ,  Jan Boris Philipp

    发明人： Thomas Happ ,  Jan Boris Philipp

    IPC分类号： G11C11/00 ,  H01L21/02

    CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2213/71

    摘要： A memory includes a first die including a first array of phase change memory cells and a second die including a second array of phase change memory cells. The second die is stacked above the first die. The memory includes lines configured to access the first die and the second die. The first die and the second die are enclosed in a single package.

    摘要翻译： 存储器包括包括第一相变存储器单元阵列的第一管芯和包括相变存储器单元的第二阵列的第二管芯。 第二模具堆叠在第一模具上方。 存储器包括被配置为访问第一管芯和第二管芯的管线。 第一个裸片和第二个裸片封装在一个封装中。

    Circuit for programming a memory element
    73.
    发明授权
    Circuit for programming a memory element 有权
    用于编程存储元件的电路

    公开(公告)号：US07564710B2

    公开(公告)日：2009-07-21

    申请号：US11742090

    申请日：2007-04-30

    申请人： Thomas Happ ,  Jan Boris Philipp ,  Ming-Hsiu Lee

    发明人： Thomas Happ ,  Jan Boris Philipp ,  Ming-Hsiu Lee

    IPC分类号： G11C11/00 ,  G11C11/56

    CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/79

    摘要： An integrated circuit includes a memory element configured to be programmed to any one of at least three resistance states and a circuit. The circuit is configured to program the memory element to a selected one of the at least three resistance states by applying a pulse to the memory element. The pulse includes one of at least three tail portions wherein each tail portion corresponds to one of the at least three resistance states.

    摘要翻译： 集成电路包括被配置为被编程为至少三个电阻状态中的任一个的存储器元件和电路。 电路被配置为通过向存储元件施加脉冲将存储器元件编程为至少三个电阻状态中的所选择的一个。 脉冲包括至少三个尾部中的一个，其中每个尾部对应于至少三个电阻状态中的一个。

    CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE
    75.
    发明申请
    CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE 失效
    当前的相位变化记忆元素结构

    公开(公告)号：US20090014704A1

    公开(公告)日：2009-01-15

    申请号：US11776301

    申请日：2007-07-11

    申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

    发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

    IPC分类号： H01L29/04

    CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

    摘要： A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

    摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层来形成电流收缩层或用作从底层绝缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

    Integrated circuit to identify read disturb condition in memory cell
    79.
    发明授权
    Integrated circuit to identify read disturb condition in memory cell 有权
    用于识别存储器单元中的读取干扰状况的集成电路

    公开(公告)号：US07405964B2

    公开(公告)日：2008-07-29

    申请号：US11494190

    申请日：2006-07-27

    申请人： Jan Boris Philipp ,  Thomas Happ

    发明人： Jan Boris Philipp ,  Thomas Happ

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/3431

    摘要： A method of operating a phase change memory array is disclosed and includes identifying a read disturb condition associated with the phase change memory array, and performing a conditional refresh operation in response to the identified read disturb condition. A phase change memory is also disclosed and includes an array of phase change memory cells, and a read disturb system configured to identify a read disturb condition and perform a refresh operation on the array in response thereto.

    摘要翻译： 公开了一种操作相变存储器阵列的方法，包括识别与相变存储器阵列相关联的读取干扰条件，以及响应于所识别的读取干扰条件执行条件刷新操作。 还公开了相变存储器，并且包括相变存储器单元的阵列，以及被配置为识别读取干扰条件并响应于该阵列执行刷新操作的读取干扰系统。

    Integrated circuit having resistive memory
    80.
    发明授权
    Integrated circuit having resistive memory 有权
    具有电阻性存储器的集成电路

    公开(公告)号：US07372725B2

    公开(公告)日：2008-05-13

    申请号：US11204201

    申请日：2005-08-15

    申请人： Jan Boris Philipp ,  Thomas Happ

    发明人： Jan Boris Philipp ,  Thomas Happ

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0061 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

    摘要： A memory device including a memory cell, a first circuit, and a second circuit. The memory cell includes phase-change material. The first circuit is configured to provide pulses to the phase-change material and to program each of more than two states into the memory cell. The second circuit is configured to sense the present state of the memory cell and provide signals that indicate the present state of the memory cell. The first circuit programs each of the more than two states into the memory cell based on the signals.

    摘要翻译： 一种包括存储单元，第一电路和第二电路的存储器件。 存储单元包括相变材料。 第一电路被配置为向相变材料提供脉冲并将多于两个状态的每一个编程到存储器单元中。 第二电路被配置为感测存储器单元的当前状态并提供指示存储器单元的当前状态的信号。 第一电路基于信号将多于两个状态的每个状态编程到存储器单元中。