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    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    73.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20100213538A1

    公开(公告)日：2010-08-26

    申请号：US12709702

    申请日：2010-02-22

    申请人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

    发明人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

    IPC分类号： H01L27/115 ,  H01L21/8246

    CPC分类号： H01L27/11578 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11582

    摘要： A memory string comprises: a first semiconductor layer having a plurality of columnar portions extending in a perpendicular direction with respect to a substrate, and joining portions joining lower ends of the plurality of columnar portions; a charge storage layer surrounding a side surface of the first semiconductor layer; and a first conductive layer surrounding a side surface of the charge storage layer and functioning as a control electrode of memory cells. A select transistor comprises: a second semiconductor layer extending upwardly from an upper surface of the columnar portions; an insulating layer surrounding a side surface of the second semiconductor layer; a second conductive layer surrounding a side surface of the insulating layer and functioning as a control electrode of the select transistors; and a third semiconductor layer formed on an upper surface of the second semiconductor layer and including silicon germanium.

    摘要翻译： 存储器串包括：第一半导体层，具有相对于衬底在垂直方向上延伸的多个柱状部分，以及连接多个柱状部分的下端的接合部分; 围绕所述第一半导体层的侧表面的电荷存储层; 以及围绕电荷存储层的侧表面并用作存储单元的控制电极的第一导电层。 选择晶体管包括：从柱状部分的上表面向上延伸的第二半导体层; 围绕所述第二半导体层的侧表面的绝缘层; 围绕所述绝缘层的侧表面并用作所述选择晶体管的控制电极的第二导电层; 以及形成在所述第二半导体层的上表面上并且包括硅锗的第三半导体层。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    74.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20100213537A1

    公开(公告)日：2010-08-26

    申请号：US12708161

    申请日：2010-02-18

    申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

    发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

    IPC分类号： H01L29/792 ,  H01L21/8239

    CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

    摘要： A memory string comprises: a pair of columnar portions; a first insulating layer surrounding a side surface of the columnar portions; a charge storage layer surrounding a side surface of the first insulating layer; a second insulating layer surrounding a side surface of the charge storage layer; and a first conductive layer surrounding a side surface of the second insulating layer. A select transistor comprises: a second semiconductor layer extending from an upper surface of the columnar portions; a third insulating layer surrounding a side surface of the second semiconductor layer; a fourth insulating layer surrounding a side surface of the third insulating layer; and a second conductive layer surrounding a side surface of the fourth insulating layer. The first semiconductor layer is formed continuously in an integrated manner with the second semiconductor layer. The first insulating layer is formed continuously in an integrated manner with the third insulating layer.

    摘要翻译： 存储器串包括：一对柱状部分; 围绕所述柱状部分的侧表面的第一绝缘层; 围绕所述第一绝缘层的侧表面的电荷存储层; 围绕电荷存储层的侧表面的第二绝缘层; 以及围绕所述第二绝缘层的侧表面的第一导电层。 选择晶体管包括：从柱状部分的上表面延伸的第二半导体层; 围绕所述第二半导体层的侧表面的第三绝缘层; 围绕所述第三绝缘层的侧表面的第四绝缘层; 以及围绕所述第四绝缘层的侧表面的第二导电层。 第一半导体层以与第二半导体层一体化的方式连续地形成。 第一绝缘层与第三绝缘层一体地形成。

    SEMICONDUCTOR MEMORY DEVICE
    76.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20100109071A1

    公开(公告)日：2010-05-06

    申请号：US12562781

    申请日：2009-09-18

    申请人： Hiroyasu TANAKA ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Yoshiaki Fukuzumi

    发明人： Hiroyasu TANAKA ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Yoshiaki Fukuzumi

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11578 ,  H01L27/11582

    摘要： A semiconductor memory device includes: a semiconductor substrate; a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked, the stacked body being provided on the semiconductor substrate; a semiconductor layer provided inside a hole formed through the stacked body, the semiconductor layer extending in stacking direction of the conductive layers and the dielectric layers; and a charge storage layer provided between the conductive layers and the semiconductor layer. The stacked body in a memory cell array region including a plurality of memory strings is divided into a plurality of blocks by slits with an interlayer dielectric film buried therein, the memory string including as many memory cells series-connected in the stacking direction as the conductive layers, the memory cell including the conductive layer, the semiconductor layer, and the charge storage layer provided between the conductive layer and the semiconductor layer, and each of the block is surrounded by the slits formed in a closed pattern.

    摘要翻译： 半导体存储器件包括：半导体衬底; 具有交替堆叠的多个导电层和多个电介质层的层叠体，所述层叠体设置在所述半导体基板上; 设置在通过所述层叠体形成的孔内的半导体层，所述半导体层沿所述导电层和所述电介质层的堆叠方向延伸; 以及设置在导电层和半导体层之间的电荷存储层。 包含多个存储器串的存储单元阵列区域中的堆叠体被埋置在其中的层间电介质膜的狭缝分成多个块，该存储串包括在堆叠方向上串联连接的存储单元作为导电 存储单元包括导电层，半导体层和设置在导电层和半导体层之间的电荷存储层，并且每个块被形成为封闭图案的狭缝包围。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
    77.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20100013049A1

    公开(公告)日：2010-01-21

    申请号：US12504959

    申请日：2009-07-17

    申请人： Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Yasuyuki Matsuoka

    发明人： Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Yasuyuki Matsuoka

    IPC分类号： H01L23/522 ,  H01L21/02 ,  H01L21/768

    CPC分类号： H01L27/11578 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A first multilayer body is formed by alternately layering dielectric films and electrode films on a substrate. Then, an end portion of the first multilayer body is processed into a staircase shape, and a first interlayer dielectric film is formed around the first multilayer body. Next, a plurality of contact holes having a diameter decreasing downward are formed in the first interlayer dielectric film so that the contact holes reach respective end portions of the electrode films. Then, a sacrificial material is buried in the contact holes. Next, a second multilayer body is formed immediately above the first multilayer body, and a second interlayer dielectric film is formed around the second multilayer body. Thereafter, a plurality of contact holes having a diameter decreasing downward are formed in the second interlayer dielectric film to communicate with the respective contact holes formed in the first interlayer dielectric film. Then, the sacrificial material is removed and a contact is buried inside the contact holes. The contact has a step difference.

    摘要翻译： 通过在基板上交替层叠电介质膜和电极膜来形成第一多层体。 然后，将第一多层体的端部加工成阶梯状，在第一层叠体的周围形成第一层间绝缘膜。 接下来，在第一层间电介质膜中形成直径减小的多个接触孔，使得接触孔到达电极膜的各个端部。 然后，牺牲材料被埋在接触孔中。 接着，在第一多层体的正上方形成第二层叠体，在第二层叠体的周围形成第二层间绝缘膜。 此后，在第二层间电介质膜中形成直径减小的多个接触孔，与形成在第一层间绝缘膜中的各接触孔连通。 然后，去除牺牲材料并将接触件埋在接触孔内。 联系人有差异。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    79.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20110127597A1

    公开(公告)日：2011-06-02

    申请号：US13003644

    申请日：2009-07-01

    申请人： Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Masaru Kito ,  Ryota Katsumata ,  Masaru Kidoh

    发明人： Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Masaru Kito ,  Ryota Katsumata ,  Masaru Kidoh

    IPC分类号： H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/7926 ,  G11C16/0466 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

    摘要： A nonvolatile semiconductor memory device with charge storage layers with high reliability is provided. A plurality of insulating films and a plurality of electrode films 14 are alternately stacked on a substrate 11, and a plurality of selection gate electrodes 17 extending in the X direction and a plurality of bit lines BL extending in the Y direction are provided thereon. U-shaped silicon members 33 are provided, each of which is constituted by a plurality of silicon pillars 31 passing through the electrode films 14 and the selection gate electrode 17, whose upper ends are connected to the bit lines BL, and a connective member 32 connecting lower parts of one pair of the silicon pillars 31 disposed in diagonal positions. The electrode film 14 of each layer is divided for the respective selection gate electrodes 17. One pair of the silicon pillars 31 connected to one another through the connective member 32 are caused to pass through the different electrode films 14 and the different selection gate electrodes 17. All of the U-shaped silicon members 33 connected commonly to one bit line BL are commonly connected to another bit line BL.

    摘要翻译： 提供具有高可靠性的电荷存储层的非易失性半导体存储器件。 多个绝缘膜和多个电极膜14交替堆叠在基板11上，并且在其上设置有沿X方向延伸的多个选择栅电极17和在Y方向上延伸的多个位线BL。 设置有U形硅构件33，每个都由通过电极膜14的多个硅柱31和其上端连接到位线BL的选择栅电极17构成，并且连接构件32 连接设置在对角位置的一对硅柱31的下部。 每个层的电极膜14被分配用于各个选择栅极电极17.使通过连接构件32彼此连接的一对硅柱31通过不同的电极膜14和不同的选择栅电极17 通常连接到一个位线BL的所有U形硅构件33共同连接到另一位线BL。