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    Nonvolatile semiconductor memory device and method of manufacturing the same
    4.
    发明授权
    Nonvolatile semiconductor memory device and method of manufacturing the same 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US08598643B2

    公开(公告)日：2013-12-03

    申请号：US13235425

    申请日：2011-09-18

    申请人： Kaori Kawasaki ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

    发明人： Kaori Kawasaki ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/7926

    摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.

    摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一导电层，第二导电层，第一电极间绝缘膜和堆叠在第一导电层上方的第三导电层，存储膜，半导体层， 绝缘构件和硅化物层。 存储膜和半导体层形成在设置在第二导电层，第一电极间绝缘膜和第三导电层中的通孔的内表面上。 绝缘构件埋设在分割第二导电层，第一电极间绝缘膜和第三导电层的狭缝中。 硅化物层形成在狭缝中的第二导电层和第三导电层的表面上。 沿着狭缝的内表面，第二导电层和第三导电层之间的距离比层叠方向长。

    Shift register memory and method of manufacturing the same
    6.
    发明授权
    Shift register memory and method of manufacturing the same 有权
    移位寄存器及其制造方法

    公开(公告)号：US09064975B2

    公开(公告)日：2015-06-23

    申请号：US13409652

    申请日：2012-03-01

    申请人： Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Hideaki Aochi

    发明人： Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Hideaki Aochi

    IPC分类号： H01L29/765 ,  H01L21/84 ,  H01L27/10 ,  H01L27/115 ,  H01L27/12 ,  G11C19/00

    CPC分类号： H01L21/84 ,  G11C19/00 ,  H01L27/10 ,  H01L27/11517 ,  H01L27/1203

    摘要： In one embodiment, a shift register memory includes first and second control electrodes extending in a first direction parallel to a surface of a substrate, and facing each other in a second direction perpendicular to the first direction. The memory further includes a plurality of first floating electrodes provided in a line on a first control electrode side between the first and second control electrodes. The memory further includes a plurality of second floating electrodes provided in a line on a second control electrode side between the first and second control electrodes. Each of the first and second floating electrodes has a planar shape which is mirror-asymmetric with respect to a plane perpendicular to the first direction.

    摘要翻译： 在一个实施例中，移位寄存器存储器包括在平行于衬底表面的第一方向上延伸的第一和第二控制电极，并且在垂直于第一方向的第二方向上彼此面对。 存储器还包括设置在第一和第二控制电极之间的第一控制电极侧的一行中的多个第一浮置电极。 存储器还包括设置在第一和第二控制电极之间的第二控制电极侧的一行中的多个第二浮置电极。 第一和第二浮动电极中的每一个具有相对于垂直于第一方向的平面镜像不对称的平面形状。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
    7.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20130221423A1

    公开(公告)日：2013-08-29

    申请号：US13599420

    申请日：2012-08-30

    申请人： Kaori Kawasaki ,  Yoshiaki Fukuzumi ,  Naoki Yasuda ,  Hideaki Aochi

    发明人： Kaori Kawasaki ,  Yoshiaki Fukuzumi ,  Naoki Yasuda ,  Hideaki Aochi

    IPC分类号： H01L29/788 ,  H01L21/20

    CPC分类号： H01L27/11556

    摘要： According to one embodiment, a nonvolatile semiconductor memory device includes an underlayer and a stacked body. The stacked body includes control gate layers and insulating layers. The device includes a channel body layer penetrating through the stacked body, and the control gate layers and the insulating layers are stacked in the stacking direction, a floating gate layer provided between each of the plurality of control gate layers and the channel body layer. The device includes a block insulating layer provided between each of the plurality of control gate layers and the floating gate layer, and includes a tunnel insulating layer provided between the channel body layer and the floating gate layer. A length of a boundary between the floating gate layer and the block insulating layer is shorter than a length of a boundary between the floating gate layer and the tunnel insulating layer.

    摘要翻译： 根据一个实施例，非易失性半导体存储器件包括底层和堆叠体。 堆叠体包括控制栅极层和绝缘层。 该器件包括穿透层叠体的沟道本体层，并且控制栅极层和绝缘层在堆叠方向上堆叠，设置在多个控制栅极层中的每一个与沟道主体层之间的浮动栅层。 该器件包括设置在多个控制栅极层和浮置栅极层中的每一个之间的块绝缘层，并且包括设置在沟道本体层和浮动栅极层之间的隧道绝缘层。 浮置栅极层与块状绝缘层之间的边界长度比浮动栅极层与隧道绝缘层的边界长度短。

    BASE MATERIAL FOR DISPLAY PANEL, METHOD FOR MANUFACTURING THE BASE MATERIAL, AND DISPLAY PANEL
    8.
    发明申请
    BASE MATERIAL FOR DISPLAY PANEL, METHOD FOR MANUFACTURING THE BASE MATERIAL, AND DISPLAY PANEL 审中-公开
    用于显示面板的基材，用于制造基底材料的方法和显示面板

    公开(公告)号：US20100014033A1

    公开(公告)日：2010-01-21

    申请号：US12448843

    申请日：2008-02-05

    申请人： Kaori Kawasaki ,  Takanori Aono

    发明人： Kaori Kawasaki ,  Takanori Aono

    IPC分类号： G02F1/13363 ,  H01J9/00

    CPC分类号： G02B5/201 ,  G02B5/3083 ,  G02F1/13363 ,  G02F1/1339 ,  G02F2001/133565 ,  G02F2001/133633 ,  G02F2201/50 ,  G02F2413/01 ,  G02F2413/11 ,  G02F2413/13

    摘要： A liquid crystal display panel in which a retardation layer is disposed in the inner side of a cell is provided. The liquid crystal display panel can improve the close adhesiveness between the retardation layer in the seal region and the base material of the liquid crystal display panel substrate constituting the liquid crystal cell, whereby leakage of light can be prevented; the rigidity of the liquid crystal cell can be improved; and the common defects of each panel can be eliminated. Also, a display panel base material for such a liquid crystal display panel and a method of manufacturing the same are provided. On a sheet-shaped base material 10, there is laminated a retardation control layer 14 using the polymerizable liquid crystal as a material in which an anisotropic phase part 14a that is polymerized and cured with use of a metal mask 70 of a structure having another frame in the inside of a frame in a state in which a polymerizable liquid crystal serving as a material is oriented and an isotropic phase part 14b that is polymerized and cured in an isotropic state in which the polymerizable liquid crystal serving as a material is not oriented are arranged to be separated in a regional manner in the plane direction thereof. The isotropic phase part 14b is disposed in a region including at least a region predetermined to be sealed on the retardation control layer 14.

    摘要翻译： 提供一种液晶显示面板，其中延迟层设置在单元的内侧。 液晶显示面板可以提高密封区域中的延迟层与构成液晶单元的液晶显示面板基板的基材之间的紧密粘合性，从而可以防止光的泄漏; 可以提高液晶单元的刚性; 并且可以消除每个面板的常见缺陷。 此外，还提供了一种用于这种液晶显示面板的显示面板基材及其制造方法。 在片状基材10上，使用可聚合液晶作为材料层叠延迟控制层14，其中使用具有另一框架的结构的金属掩模70聚合和固化的各向异性相部分14a 在作为材料的聚合性液晶取向的状态下的框架内部，以各向同性状态聚合固化的各向同性状态的各向异性状态，其中作为材料的取向的聚合性液晶不是取向的各向同性相部分14b， 被布置为在其平面方向上以区域方式分离。 各向同性相部分14b设置在至少包括预定密封在延迟控制层14上的区域的区域中。