公开(公告)号：US20070224745A1

公开(公告)日：2007-09-27

申请号：US11308390

申请日：2006-03-21

Applicant: Hui-Chen Chang ,  Tony Lin ,  Brook Hsu ,  Cyrus LW Chen ,  Meng-Lin Lee ,  Wei-Tsun Shiau

Inventor： Hui-Chen Chang ,  Tony Lin ,  Brook Hsu ,  Cyrus LW Chen ,  Meng-Lin Lee ,  Wei-Tsun Shiau

IPC: H01L21/8234

CPC classification number: H01L21/28114 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

Abstract: A semiconductor device including a substrate, a gate dielectric layer, a gate, a pair of source/drain regions and a stressed layer is disclosed. The gate dielectric layer is disposed on the substrate and the gate whose top area is larger than its bottom area is disposed on the gate dielectric layer. The source/drain regions are disposed in the substrate next to the sidewalls of the gate. The stressed layer is disposed on the substrate to cover the gate and the source/drain regions.

Abstract translation: 公开了一种包括衬底，栅介质层，栅极，一对源极/漏极区域和应力层的半导体器件。 栅极电介质层设置在基板上，并且顶部区域大于其底部区域的栅极设置在栅极介电层上。 源极/漏极区域设置在邻近栅极的侧壁的衬底中。 应力层设置在基板上以覆盖栅极和源极/漏极区域。

公开(公告)号：US20050093103A1

公开(公告)日：2005-05-05

申请号：US10697771

申请日：2003-10-29

Applicant: Yoyi Gong ,  Tony Lin ,  Jung-Tsung Tseng ,  Abula Yu

Inventor： Yoyi Gong ,  Tony Lin ,  Jung-Tsung Tseng ,  Abula Yu

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224

Abstract: A shallow trench isolation (STI) structure and fabricating method thereof is provided. A substrate is provided. A patterned mask layer is formed over the substrate. Using the patterned mask layer as an etching mask, the substrate is patterned to form a trench. A nitridation process is performed to form a silicon nitride liner on the surface of the trench. An insulating material is deposited to fill the trench. Since the silicon nitride liner within the STI is very thin, residual stress within the substrate is reduced, and the silicon nitride liner has very little or negligible impact on the trench aspect ratio.

Abstract translation: 提供浅沟槽隔离（STI）结构及其制造方法。 提供基板。 在衬底上形成图案化掩模层。 使用图案化掩模层作为蚀刻掩模，将衬底图案化以形成沟槽。 进行氮化处理以在沟槽的表面上形成氮化硅衬垫。 沉积绝缘材料以填充沟槽。 由于STI内的氮化硅衬垫非常薄，衬底内的残余应力减小，并且氮化硅衬垫对沟槽纵横比的影响很小或可忽略不计。

公开(公告)号：US06503807B2

公开(公告)日：2003-01-07

申请号：US09803893

申请日：2001-03-13

Applicant: Chin-Lai Chen ,  Tony Lin ,  Jih-Wen Chou

Inventor： Chin-Lai Chen ,  Tony Lin ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/4991 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66583

Abstract: A MOS transistor includes a substrate, an insulation layer, a gate and a dielectric layer. The substrate includes a drain and a source separately positioned on the surface of the substrate. The insulation layer is positioned on the surface of the substrate between the drain and the source. The gate includes a conducting layer positioned on the insulation layer having a bottom side, a top side, a left side and a right side, and a metallic silicide layer positioned on the top side of the conducting layer wherein the width of the metallic silicide layer is greater than that of the bottom side of the conducting layer. The dielectric layer covers the drain, the source and the metallic silicide layer. The transistor includes at least one empty side slot positioned between the dielectric layer and the left side or right side of the conducting layer below the metallic silicide layer.

Abstract translation: MOS晶体管包括基板，绝缘层，栅极和电介质层。 衬底包括分别位于衬底的表面上的漏极和源极。 绝缘层位于漏极和源极之间的衬底表面上。 栅极包括位于具有底侧，顶侧，左侧和右侧的绝缘层上的导电层和位于导电层顶侧的金属硅化物层，其中金属硅化物层的宽度 大于导电层底面的面积。 电介质层覆盖漏极，源极和金属硅化物层。 晶体管包括至少一个位于电介质层与金属硅化物层下方的导电层的左侧或右侧之间的空侧槽。

公开(公告)号：US06365468B1

公开(公告)日：2002-04-02

申请号：US09598192

申请日：2000-06-21

Applicant: Wen-Kuan Yeh ,  Tony Lin ,  Chih-Yung Lin

Inventor： Wen-Kuan Yeh ,  Tony Lin ,  Chih-Yung Lin

IPC: H01L21336

CPC classification number: H01L21/823835 ,  H01L21/2807 ,  H01L21/823878 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method for forming doped p-type gate is disclosed as the following description. The method includes that, firstly, a semiconductor substrate is provided. The semiconductor substrate is etched to form a concave portion as a shallow trench isolation. A first silicon dioxide is filled into the shallow trench isolation. A n-type well is formed into the semiconductor substrate. A silicon germanium layer, named as the doped p-type layer is formed on the surface of semiconductor substrate and the surface of shallow trench isolation. A silicon nitride layer, named as the anti-reflection layer is formed on the surface of silicon germanium layer. The portions of silicon nitride layer and the portions of silicon germanium layer are etched as a gate region. The source/drain extension is formed. A second silicon dioxide layer is deposited over the surface of semiconductor substrate and the surface of nitride layer. The second silicon dioxide layer is etched as a spacer beside the sidewall of gate region. A source/drain region is formed into the semiconductor substrate. The silicon nitride layer is removed. Finally, salicide region is formed into the source/drain region and upon the surface of silcion layer to complete the silicon gate structure.

Abstract translation: 公开了用于形成掺杂p型栅极的方法，如以下描述。 该方法包括：首先提供半导体衬底。 蚀刻半导体衬底以形成作为浅沟槽隔离的凹部。 将第一个二氧化硅填充到浅沟槽隔离中。 n型阱形成在半导体衬底中。 在半导体衬底的表面和浅沟槽隔离的表面上形成被称为掺杂p型层的硅锗层。 在硅锗层的表面上形成称为抗反射层的氮化硅层。 蚀刻氮化硅层的部分和硅锗层的部分作为栅极区域。 源/漏扩展形成。 在半导体衬底的表面和氮化物层的表面上沉积第二二氧化硅层。 将第二二氧化硅层作为栅极区域的侧壁旁边的间隔物进行蚀刻。 源极/漏极区域形成为半导体衬底。 去除氮化硅层。 最后，将硅化物区域形成为源极/漏极区域，并在硅酸盐层的表面形成硅栅极结构。

公开(公告)号：US06350656B1

公开(公告)日：2002-02-26

申请号：US09495249

申请日：2000-01-31

Applicant: Jung-Chun Lin ,  Tony Lin ,  Jih-Wen Chou

Inventor： Jung-Chun Lin ,  Tony Lin ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/66575 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/41783 ,  H01L29/665

Abstract: A SEG combined with tilt implant method for forming semiconductor device is disclosed. The method includes providing a semiconductor structure which comprises an active area in between isolation regions in a substrate with the active area having a gate electrode formed thereon, wherein a spacer is formed on the sidewall of said gate electrode. Then, selective epitaxial growth regions are formed on the active area and the gate electrode. Next, the active area is implanted with an angle to form source/drain regions beside the bottom edge of the gate electrode. Then, the salicide process and backend processes are performed.

Abstract translation: 公开了一种结合用于形成半导体器件的倾斜植入方法的SEG。 该方法包括提供半导体结构，该半导体结构包括在衬底中的隔离区域之间的有源区域，其中有源区域上形成有栅电极，其中间隔物形成在所述栅电极的侧壁上。 然后，在有源区和栅电极上形成选择性外延生长区。 接下来，以一角度植入有源区域，以在栅电极的底部边缘旁边形成源极/漏极区域。 然后，执行自杀化合物处理和后端处理。

公开(公告)号：US06319807B1

公开(公告)日：2001-11-20

申请号：US09498861

申请日：2000-02-07

Applicant: Wen-Kuan Yeh ,  Tony Lin

Inventor： Wen-Kuan Yeh ,  Tony Lin

IPC: H01L213205

CPC classification number: H01L29/66553 ,  H01L21/28123 ,  H01L29/66537 ,  H01L29/66545

Abstract: A method for forming semiconductor devices is disclosed. The method of the present invention includes providing a semiconductor substrate, followed by forming shallow trench isolation (STI) process, and then a dummy gate is formed by silicon nitride layer which is deposited and defined. With appropriate wet etching, this dummy poly can be removed. After local punch-through implantation, reverse offset spacer is formed to reduce Cgd (capacitance is between gate and drain) and poly-CD (critical dimension). Polysilicon is deposited followed by polysilicon CMP. After thick Ti-salicidation, the usual CMOS (Complementary Metal-Oxide-Semiconductor) processes are proceeded.

Abstract translation: 公开了一种用于形成半导体器件的方法。 本发明的方法包括提供半导体衬底，然后形成浅沟槽隔离（STI）工艺，然后通过沉积和限定的氮化硅层形成虚拟栅极。 通过适当的湿法蚀刻，可以除去该假聚聚物。 在局部穿通植入之后，形成反向偏移间隔物以减少Cgd（电容在栅极和漏极之间）和聚-CD（临界尺寸）。 沉积多晶硅，然后沉积多晶硅CMP。 在厚的Ti-盐化之后，进行通常的CMOS（互补金属氧化物半导体）工艺。

公开(公告)号：US06274450B1

公开(公告)日：2001-08-14

申请号：US09398733

申请日：1999-09-17

Applicant: Tony Lin ,  Coming Chen ,  Jih-Wen Chou

Inventor： Tony Lin ,  Coming Chen ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for manufacturing metal oxide semiconductor field effect transistor is disclosed. The metal oxide semiconductor field effect transistor is formed by a specific fabricating process that disadvantages of thermal damage are effectively prevented. According to the method, first a substrate is provided. Second, an isolation and a well are formed in the substrate, and then a first dielectric layer, a conductive layer and an anti-reflection coating layer are formed on the substrate sequentially. Third, a gate is formed on the substrate, and then a source and a drain are formed in the substrate and a spacer is formed on the substrate. Fourth, both source and drain are annealed, and then a first salicide is formed on both source and drain. Fifth, a second dielectric layer is formed on the substrate and is planarized, where the anti-reflecting coating layer is totally removed and the conductive layer is partially removed. Sixth, a second salicide is formed on the conductive layer. Seventh, the spacer is removed and both a halo and a source drain extension are formed in substrate. Finally, a third dielectric layer is formed on second dielectric layer. Obviously, one main characteristic of the invention is both source drain extension and halo are formed after a plurality of thermal processes such as deposition, annealing and formation of salicide.

Abstract translation: 公开了一种用于制造金属氧化物半导体场效应晶体管的方法。 金属氧化物半导体场效应晶体管通过具体的制造工艺形成，有效地防止了热损伤的缺点。 根据该方法，首先提供基板。 第二，在衬底中形成隔离和阱，然后依次在衬底上形成第一介电层，导电层和抗反射涂层。 第三，在衬底上形成栅极，然后在衬底中形成源极和漏极，并在衬底上形成间隔物。 第四，源极和漏极都被退火，然后在源极和漏极上形成第一自对准硅化物。 第五，在基板上形成第二电介质层并进行平面化处理，其中防反射涂层被完全去除并且导电层被部分去除。 第六，在导电层上形成第二个自对准硅化物。 第七，去除间隔物，并且在衬底中形成卤素和源极漏极延伸。 最后，在第二电介质层上形成第三电介质层。 显然，本发明的一个主要特征是源极漏极延伸，并且在诸如沉积，退火和形成硅化物的多个热处理之后形成卤素。

公开(公告)号：US06187645B1

公开(公告)日：2001-02-13

申请号：US09233354

申请日：1999-01-19

Applicant: Tony Lin ,  Coming Chen ,  Jih-Wen Chou

Inventor： Tony Lin ,  Coming Chen ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/28035

Abstract: A method for manufacturing semiconductor device. The method includes the steps of providing a substrate that has a gate structure thereon, and then forming offset spacers on the sidewalls of the gate structure. Thereafter, a thin oxide annealing operation is conducted, and then a first ion implantation is carried out using the gate structure and the offset spacers as a mask to form lightly doped drain regions in the substrate. Subsequently, secondary spacers are formed on the exterior sidewalls of the offset spacers. Finally, a second ion implantation is carried out using the gate structure, the offset spacers and the secondary spacers as a mask to form source/drain regions within the lightly doped drain regions.

Abstract translation: 一种半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底，然后在栅极结构的侧壁上形成偏置间隔物。 此后，进行薄氧化物退火操作，然后使用栅极结构和偏移间隔物作为掩模进行第一离子注入，以在衬底中形成轻掺杂的漏极区。 随后，在偏置间隔物的外侧壁上形成二次间隔物。 最后，使用栅极结构，偏移间隔物和次级间隔物作为掩模进行第二离子注入，以在轻掺杂漏极区内形成源/漏区。

公开(公告)号：US06177336B1

公开(公告)日：2001-01-23

申请号：US09187245

申请日：1998-11-06

Applicant: Tony Lin ,  Wen-Kuan Yeh ,  Coming Chen ,  Jih-Wen Chou

Inventor： Tony Lin ,  Wen-Kuan Yeh ,  Coming Chen ,  Jih-Wen Chou

IPC: H01L214763

CPC classification number: H01L29/66545 ,  H01L29/66537

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is provided. The method has steps of sequentially forming an oxide layer, a polysilicon layer and a cap layer on a semiconductor substrate to form a first-stage gate. An interchangeable source/drain region with a lightly doped drain (LDD) structure is formed in the substrate at each side of the first-stage gate. An insulating layer is formed over the substrate, and is planarized so as to exposed the cap layer. Removing the exposed cap layer forms an opening that exposes the polysilicon layer. Using the insulating layer as a mask, a self-aligned selective local implantation process is performed to form a threshold-voltage doped region and an anti-punch-through doped region below the oxide layer in the substrate. A conductive layer is formed over the substrate to fill the opening. A chemical mechanical polishing process is performed to expose the insulating layer so that a remaining portion of the conductive layer fills the opening to form together with the polysilicon layer and the oxide layer to serve as an gate structure.

Abstract translation: 提供一种制造金属氧化物半导体（MOS）晶体管的方法。 该方法具有在半导体衬底上依次形成氧化物层，多晶硅层和覆盖层以形成第一级栅极的步骤。 在第一级栅极的每一侧的衬底中形成具有轻掺杂漏极（LDD）结构的可互换的源极/漏极区域。 绝缘层形成在衬底上，并被平坦化以使盖层露出。 去除暴露的盖层形成暴露多晶硅层的开口。 使用绝缘层作为掩模，执行自对准选择性局部注入工艺以在衬底中的氧化物层下方形成阈值电压掺杂区域和抗穿通掺杂区域。 导电层形成在衬底上以填充开口。 执行化学机械抛光工艺以暴露绝缘层，使得导电层的剩余部分填充开口以与多晶硅层和氧化物层一起形成以用作栅极结构。

公开(公告)号：US06174778B1

公开(公告)日：2001-01-16

申请号：US09212055

申请日：1998-12-15

Applicant: Coming Chen ,  Tony Lin ,  Jih-Wen Chou

Inventor： Coming Chen ,  Tony Lin ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083

Abstract: A method of fabricating a metal oxide semiconductor includes formation of a gate on a substrate. A source/drain extension is formed beside the gate in the substrate. An ion implantation step is performed to implant heavy impurities with a low diffusion coefficient in the substrate. A heavily doped halo region is formed in the substrate below the source/drain extension. A tilt-angled halo implantation step is performed to form a halo-implanted region in the substrate to the side of the source/drain extension below the gate.

Abstract translation: 制造金属氧化物半导体的方法包括在基板上形成栅极。 在衬底的栅极旁边形成源极/漏极延伸部。 进行离子注入步骤以在衬底中植入具有低扩散系数的重杂质。 在源极/漏极延伸部下方的衬底中形成重掺杂的卤素区域。 进行倾斜角度的晕圈注入步骤以在衬底中的栅极下方的源极/漏极延伸侧形成卤素注入区域。