公开(公告)号：US07754540B2

公开(公告)日：2010-07-13

申请号：US12395506

申请日：2009-02-27

申请人： Vladislav Vashchenko ,  Peter J. Hopper

发明人： Vladislav Vashchenko ,  Peter J. Hopper

IPC分类号： H01L21/332

CPC分类号： H01L27/0259

摘要： A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors.

摘要翻译： 用于交流（DIAC）静电放电（ESD）保护电路的二极管形成在利用非常薄的集电极区域的硅锗（SiGe）合金双极晶体管（HBT）工艺中。 通过利用SiGe晶体管的基极结构和发射极结构，提供一对待保护焊盘的ESD保护。

公开(公告)号：US07705403B1

公开(公告)日：2010-04-27

申请号：US11324455

申请日：2006-01-03

申请人： Vladislav Vashchenko ,  Yuri Mirgorodski ,  Peter J. Hopper

发明人： Vladislav Vashchenko ,  Yuri Mirgorodski ,  Peter J. Hopper

IPC分类号： H01L23/62

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： In a LVTSCR or snapback NMOS ESD structure, low voltage protection as well as higher voltage protection is provided by introducing a floating gate that capacitively couples with the control gate of the ESD structure and programming the floating gate to have different charges on it as desired.

摘要翻译： 在LVTSCR或快速恢复型NMOS ESD结构中，通过引入与ESD结构的控制栅极电容耦合的浮动栅极，并根据需要对浮动栅极进行编程，从而提供低电压保护以及更高的电压保护。

公开(公告)号：US07528012B1

公开(公告)日：2009-05-05

申请号：US11508495

申请日：2006-08-22

申请人： Peter J. Hopper ,  Iouri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

发明人： Peter J. Hopper ,  Iouri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

IPC分类号： H01L21/00

CPC分类号： H01L29/78606 ,  H01L23/3677 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus and method for a heat sink to dissipate the heat sourced by the encapsulated transistors in a SOI wafer. The apparatus includes a transistor formed in the active silicon layer of the wafer. The active surface is formed over an oxide layer and a bulk silicon layer. A heat sink is formed in the bulk silicon layer and configured to sink heat through the bulk silicon layer, to the back surface of the wafer. After the transistor is fabricated, the heat sink is formed by masking, patterning and etching the back surface of the wafer to form plugs in the bulk silicon layer. The plug extends through the thickness of the bulk layer to the oxide layer. Thereafter, the plug is filled with a thermally conductive material, such as a metal or DAG (thermally conductive paste). During operation, heat from the transistor is dissipated through the heat sink. In various embodiments of the invention, the plug hole is formed using either an anisotropic plasma or wet etch.

摘要翻译： 散热器散热由SOI晶片中的封装晶体管产生的热量的装置和方法。 该装置包括形成在晶片的有源硅层中的晶体管。 活性表面形成在氧化物层和体硅层上。 在体硅层中形成散热器，并且构造成将热量通过体硅层吸收到晶片的背面。 在制造晶体管之后，通过掩模，图案化和蚀刻晶片的背面来形成散热器，以在体硅层中形成插塞。 塞子延伸穿过本体层的厚度到氧化物层。 此后，塞子填充有导热材料，例如金属或DAG（导热浆）。 在运行期间，来自晶体管的热量通过散热器消散。 在本发明的各种实施例中，插塞孔使用各向异性等离子体或湿蚀刻形成。

公开(公告)号：US07422952B1

公开(公告)日：2008-09-09

申请号：US11799954

申请日：2007-05-03

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/7322 ,  H01L27/0259 ,  H01L29/0821

摘要： A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.

摘要翻译： 将一个压载区域放置在双极结晶体管的基极区域和集电极触点之间，以将热点移离晶体管的集电极触点。 将热点从集电极接触点移开可防止集电极接触在静电放电（ESD）脉冲期间熔化。

公开(公告)号：US07375393B1

公开(公告)日：2008-05-20

申请号：US11044511

申请日：2005-01-27

申请人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko

发明人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L29/42324

摘要： An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.

公开(公告)号：US07196361B1

公开(公告)日：2007-03-27

申请号：US10734921

申请日：2003-12-12

申请人： Vladislav Vashchenko ,  Willem Kindt ,  Peter J. Hopper

发明人： Vladislav Vashchenko ,  Willem Kindt ,  Peter J. Hopper

IPC分类号： H01R29/747 ,  H01R29/87

CPC分类号： H01L27/0262

摘要： In a high voltage ESD protection solution, a plurality of DIACs are connected together to define a cascaded structure with isolation regions provided to prevent n-well and p-well punch through. An p-ring surrounds the DIACs and provides a ground for the substrate in which the DIACs are formed.

摘要翻译： 在高电压ESD保护解决方案中，多个DIAC连接在一起以限定提供隔离区域的级联结构，以防止n阱和p阱穿通。 一个p环环绕着DIAC，并为形成DIAC的衬底提供了一个接地。

公开(公告)号：US07126168B1

公开(公告)日：2006-10-24

申请号：US10821287

申请日：2004-04-09

申请人： Vladislav Vashchenko ,  Peter J. Hopper

发明人： Vladislav Vashchenko ,  Peter J. Hopper

IPC分类号： H01L29/49

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： The turn on time of an electrostatic discharge (ESD) structure, such as a silicon controlled rectifier (SCR), a low-voltage triggering SCR (LVTSCR), and a bipolar SCR (BSCR), is reduced by turning on the structure in two steps: a first step that locally turns on the pnp and npn transistors, and a second step that, over time, fully turns on the structure.

摘要翻译： 静电放电（ESD）结构的导通时间，例如可控硅整流器（SCR），低电压触发SCR（LVTSCR）和双极SCR（BSCR））通过打开两个结构 步骤：第一步，在本地打开pnp和npn晶体管，第二步，随着时间的推移，完全打开结构。

公开(公告)号：US07115951B1

公开(公告)日：2006-10-03

申请号：US10234817

申请日：2002-09-04

申请人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek ,  Yuri Mirgorodsky

发明人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek ,  Yuri Mirgorodsky

IPC分类号： H01L23/62

CPC分类号： H01L29/4238 ,  H01L29/78

摘要： In a triggering ESD protection structure, the triggering voltage is reduced by introducing one or more corners or spikes into the p-n breakdown junction. This may be done by providing a polygate with a zig-zag pattern to define triangular corners in the drain or anode of the structure.

摘要翻译： 在触发ESD保护结构中，通过将一个或多个拐角或尖峰引入p-n击穿结中来减小触发电压。 这可以通过提供具有之字形图案的多晶硅浇口来在结构的漏极或阳极中限定三角形拐角来完成。

公开(公告)号：US07067852B1

公开(公告)日：2006-06-27

申请号：US09660386

申请日：2000-09-12

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Manuel Carneiro

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Manuel Carneiro

IPC分类号： H01L29/74 ,  H01L23/62

CPC分类号： H01L27/0262 ,  H01L29/86 ,  H01L29/8618 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection structure includes a semiconductor substrate of a first conductivity type, and first and second well regions of a second conductivity type disposed in the substrate. The first and second well regions are separated by a gap region of the substrate. Also included are first and second floating regions (of the second conductivity type) disposed in the first and second well regions adjacent to the gap region, respectively. The ESD protection structure also includes first and second contact regions of the first conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively. The ESD protection structure also includes first and second contact regions of the second conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively.

摘要翻译： ESD保护结构包括第一导电类型的半导体衬底和设置在衬底中的第二导电类型的第一和第二阱区。 第一和第二阱区域被衬底的间隙区域分开。 还包括设置在与间隙区域相邻的第一和第二阱区域中的第一和第二浮动区域（第二导电类型）。 ESD保护结构还包括分别设置在第一和第二阱区上并分别与第一和第二浮动区分开的第一导电类型的第一和第二接触区域。 ESD保护结构还包括分别设置在第一和第二阱区上并分别与第一和第二浮动区隔开的第二导电类型的第一和第二接触区域。

公开(公告)号：US07064397B1

公开(公告)日：2006-06-20

申请号：US10649989

申请日：2003-08-27

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Ann Concannon ,  Marcel Ter Beek

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Ann Concannon ,  Marcel Ter Beek

IPC分类号： H01L29/76

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the collector of the NPN transistor between the emitter and collector of the PNP transistor.

摘要翻译： 当诸如ESD脉冲之类的高压被放置在包括NPN晶体管和连接到NPN晶体管的PNP晶体管的可控硅整流器上时，整流器的两个区域之间产生冲击的可能性 通过在PNP晶体管的发射极和集电极之间形成NPN晶体管的集电极而大大减小。