公开(公告)号：US20130039717A1

公开(公告)日：2013-02-14

申请号：US13636570

申请日：2011-03-23

申请人： Yuji Sasaki

发明人： Yuji Sasaki

IPC分类号： F16B19/10

CPC分类号： F16B19/1081 ,  Y10T24/309

摘要： A fastening member has a head part, a shaft part, a thinly formed flange extending in a straight shape from an outer perimeter of the head part, and a coupling device (for example, head part of a grommet). A part has a through-hole, and a wall part positioned on an outer perimeter of the through hole and extending toward the direction of insertion of the shaft part. A base has an installation hole allowing insertion of the shaft part. When the base and the part are bound by insertion of the shaft part, the flange is pressed against the wall part and becomes in a bent-back state.

摘要翻译： 紧固构件具有头部，轴部，从头部的外周延伸成直线形状的薄形凸缘，以及联接装置（例如，护环的头部）。 一部分具有通孔和位于通孔的外周上且朝着轴部的插入方向延伸的壁部分。 基座具有允许轴部插入的安装孔。 当基部和部分通过插入轴部分而被限制时，凸缘被压靠在壁部上并变成弯曲状态。

公开(公告)号：US08212312B2

公开(公告)日：2012-07-03

申请号：US13355280

申请日：2012-01-20

申请人： Yuji Sasaki

发明人： Yuji Sasaki

IPC分类号： H01L29/66

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/0688 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66712

摘要： Disclosed herein is a semiconductor device including: a first conductivity type semiconductor base body; a first conductivity type pillar region; second conductivity type pillar regions; element and termination regions provided in the first and second conductivity type pillar regions, transistors being formed in the element region, and no transistors being formed in the termination region; body regions; a gate insulating film; gate electrodes; source regions; and body potential extraction regions, wherein voids are formed in the second conductivity type pillar regions of the termination region.

公开(公告)号：US08115250B2

公开(公告)日：2012-02-14

申请号：US12687662

申请日：2010-01-14

申请人： Yuji Sasaki

发明人： Yuji Sasaki

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/0688 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66712

摘要： Disclosed herein is a semiconductor device including: a first conductivity type semiconductor base body; a first conductivity type pillar region; second conductivity type pillar regions; element and termination regions provided in the first and second conductivity type pillar regions, transistors being formed in the element region, and no transistors being formed in the termination region; body regions; a gate insulating film; gate electrodes; source regions; and body potential extraction regions, wherein voids are formed in the second conductivity type pillar regions of the termination region.

摘要翻译： 本发明公开了一种半导体器件，包括：第一导电型半导体基体; 第一导电型支柱区域; 第二导电型支柱区域; 设置在第一和第二导电型柱区域中的元件和端接区域，晶体管形成在元件区域中，并且在端接区域中不形成晶体管; 身体区域 栅极绝缘膜; 栅电极; 源区; 以及体电位提取区域，其中在端接区域的第二导电型柱区域中形成空隙。

公开(公告)号：US08106447B2

公开(公告)日：2012-01-31

申请号：US12502067

申请日：2009-07-13

申请人： Hiroki Hozumi ,  Yuji Sasaki ,  Shusaku Yanagawa

发明人： Hiroki Hozumi ,  Yuji Sasaki ,  Shusaku Yanagawa

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

摘要： Disclosed herein is a semiconductor device, including: a first semiconductor region of a first conductivity type; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity type alternately provided; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the first conductivity type; and control electrodes each provided within a trench through an insulating film, a sidewall of the trench being formed so as to contact each of the third semiconductor region and the fourth semiconductor region.

摘要翻译： 本文公开了一种半导体器件，包括：第一导电类型的第一半导体区域; 具有交替设置的具有第一导电类型的第一支柱区域和第二导电类型的第二柱状区域的第二半导体区域; 第二导电类型的第三半导体区域; 第一导电类型的第四半导体区域; 以及控制电极，每个控制电极通过绝缘膜设置在沟槽内，所述沟槽的侧壁形成为与第三半导体区域和第四半导体区域接触。

公开(公告)号：USD641609S1

公开(公告)日：2011-07-19

申请号：US29347731

申请日：2010-04-27

申请人： Naofumi Yagame ,  Yuji Sasaki

设计人： Naofumi Yagame ,  Yuji Sasaki

公开(公告)号：US20110057256A1

公开(公告)日：2011-03-10

申请号：US12869952

申请日：2010-08-27

申请人： Yuji Sasaki

发明人： Yuji Sasaki

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/66712

摘要： A semiconductor device includes a first conductive type semiconductor substrate; a first conductive type semiconductor region provided thereon in which first conductive type first pillar regions and second conductive type second pillar regions alternately arranged; second conductive type second semiconductor regions provided on second pillar regions in an element region to be in contact with first pillar regions therein; gate electrodes each provided on adjacent second semiconductor regions and on one of the first pillar region interposed therebetween; third semiconductor regions functioning as a first conductive type source region provided in parts of the second semiconductor regions located under side portions of the gate electrodes; and a second conductive type resurf region which is a part of a terminal region surrounding the element region and which is provided on first pillar regions and second pillar regions in the part of the terminal regions.

摘要翻译： 半导体器件包括第一导电类型半导体衬底; 设置在其上的第一导电型第一柱状区域和第二导电型第二柱状区域交替布置的第一导电型半导体区域; 第二导电型第二半导体区域，设置在与其中的第一柱状区域接触的元件区域中的第二柱状区域上; 每个栅电极设置在相邻的第二半导体区域上并且在其间的第一柱区域中的一个上; 第三半导体区域用作第一导电型源极区域，设置在位于栅电极的侧部下方的第二半导体区域的部分中; 以及作为围绕元件区域的端子区域的一部分并且设置在端子区域的一部分中的第一柱状区域和第二柱状区域上的第二导电型复原区域。

公开(公告)号：US07157320B2

公开(公告)日：2007-01-02

申请号：US10816307

申请日：2004-04-01

申请人： Yuji Sasaki

发明人： Yuji Sasaki

IPC分类号： H01L21/338 ,  H01L21/337 ,  H01L21/8238 ,  H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/66287 ,  H01L29/7322

摘要： A semiconductor device comprising: a first insulating film formed on a semiconductor substrate; a semiconductor layer at least a part of which is formed on the first insulating film; a second insulating film comprising a non-doped silicon oxide film and formed on the semiconductor layer; a third insulating film comprising a silicon oxide film containing at least phosphorus formed on the second insulating film; and a fourth insulating film comprising a non-doped silicon oxide film formed on the third insulating film.

摘要翻译： 一种半导体器件，包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其至少一部分形成在所述第一绝缘膜上; 第二绝缘膜，包括非掺杂氧化硅膜并形成在所述半导体层上; 第三绝缘膜，包括至少含有形成在第二绝缘膜上的磷的氧化硅膜; 以及第四绝缘膜，其包括形成在第三绝缘膜上的非掺杂氧化硅膜。

公开(公告)号：US06840228B2

公开(公告)日：2005-01-11

申请号：US10725664

申请日：2003-12-02

申请人： Koichiro Yomogida ,  Futoshi Nakano ,  Yusuke Saigo ,  Yuji Sasaki

发明人： Koichiro Yomogida ,  Futoshi Nakano ,  Yusuke Saigo ,  Yuji Sasaki

IPC分类号： F02M37/00 ,  F02D41/38 ,  F02M47/02 ,  F02M55/02 ,  F02M51/00

CPC分类号： F02D41/3836 ,  F02D41/3845 ,  F02D2041/1432 ,  F02D2200/0602 ,  F02D2250/04 ,  F02D2250/14

摘要： The detected values of a common rail pressure that were detected by a pressure sensor are read within crank angle periods Δt which are at least not more than half of a pumping cycle ΔT of a supply pump, the values detected within one pumping cycle preceding a reading time (for example, S(1), S(0), . . . S(−4)) are averaged during each of the reading times, and the value thus obtained (for example, Pav(1)) is used as a common rail pressure after averaging processing, which is a representative value or a control value of the actual common rail pressure. The feedback control of common rail pressure is executed by using the values of common rail pressure after averaging processing thus computed by moving averaging. Consequently, the actual common rail pressure is converted into values suitable for control, and the feedback control of common rail pressure is executed with higher accuracy.

摘要翻译： 在压力传感器检测到的共轨压力的检测值在曲轴角度周期Deltat内被读取，曲柄角周期Deltat至少不超过供应泵的泵送周期DeltaT的一半，在读数之前的一个泵送循环中检测到的值 时间（例如，S（1），S（0），... S（-4））在每个读取时间期间被平均，并且将由此获得的值（例如，Pav（1））用作 平均处理之后的共轨压力，其是实际共轨压力的代表值或控制值。 通过使用通过移动平均计算的平均化处理后的共轨压力值来执行共轨压力的反馈控制。 因此，将实际共轨压力转换为适合于控制的值，并且以更高的精度执行共轨压力的反馈控制。

公开(公告)号：US06271488B1

公开(公告)日：2001-08-07

申请号：US09453552

申请日：1999-12-03

申请人： Yuji Sasaki

发明人： Yuji Sasaki

IPC分类号： H01H900

CPC分类号： H01H25/006 ,  H01H25/008 ,  H01H2019/146

摘要： A switch mechanism includes a control member whose axis of rotation is longitudinal, a pair of supporting members to support the control member rotatably and also movably in a direction perpendicular to the axis of rotation, a first detector to detect a rotation of the control member, a second detector to detect a movement of the control member in a direction perpendicular to the axis of rotation, and a third detector to detect a movement of the control member along the axis of rotation.

摘要翻译： 开关机构包括其旋转轴线为纵向的控制构件，一对支撑构件，其可旋转地支撑控制构件，并且也可在垂直于旋转轴线的方向上移动;第一检测器，用于检测控制构件的旋转; 第二检测器，用于检测控制构件在垂直于旋转轴线的方向上的移动;以及第三检测器，用于检测控制构件沿着旋转轴线的移动。

公开(公告)号：US5978181A

公开(公告)日：1999-11-02

申请号：US947114

申请日：1997-10-08

申请人： Masaaki Niijima ,  Yuji Sasaki

发明人： Masaaki Niijima ,  Yuji Sasaki

IPC分类号： G11B5/008 ,  G11B5/012 ,  G11B5/39 ,  G11B5/40

CPC分类号： G11B5/3903 ,  G11B5/40 ,  G11B5/00813 ,  G11B5/012

摘要： A magnetoresistive magnetic head comprises a first magnetic shielding layer formed on an underlying layer, a first nonmagnetic insulating layer formed on the first magnetic shielding layer, a magnetoresistive device formed on the first nonmagnetic insulating layer, first and second leads formed on the first nonmagnetic insulating layer to be connected to both sides of the magnetoresistive device respectively, a second nonmagnetic insulating layer formed to cover the first and second leads and the magnetoresistive device, a second magnetic shielding layer formed on the second nonmagnetic insulating layer to be positioned over the magnetoresistive device, and a resistor element buried in at least one of the first and second nonmagnetic insulating layers to electrically connect the first lead to either the first magnetic shielding layer or the second magnetic shielding layer.

摘要翻译： 磁阻磁头包括形成在下层上的第一磁屏蔽层，形成在第一磁屏蔽层上的第一非磁性绝缘层，形成在第一非磁性绝缘层上的磁阻器件，形成在第一非磁性绝缘层上的第一和第二引线 层，其分别连接到磁阻器件的两侧，形成为覆盖第一和第二引线和磁阻器件的第二非磁性绝缘层，形成在第二非磁性绝缘层上以定位在磁阻器件上的第二磁屏蔽层 以及埋在第一和第二非磁性绝缘层中的至少一个中的电阻元件，以将第一引线电连接到第一磁屏蔽层或第二磁屏蔽层。