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238 条记录 (耗时 0.049 秒)

    Method of manufacturing an electrically erasable programmable read-only memory (EEPROM)
    71.
    发明授权
    Method of manufacturing an electrically erasable programmable read-only memory (EEPROM) 有权
    制造电可擦除可编程只读存储器（EEPROM）的方法

    公开(公告)号：US07504294B2

    公开(公告)日：2009-03-17

    申请号：US10881180

    申请日：2004-07-01

    申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

    发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

    摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

    摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

    Semiconductor device with a selection gate and a peripheral gate
    72.
    发明授权
    Semiconductor device with a selection gate and a peripheral gate 有权
    具有选择栅极和外围栅极的半导体器件

    公开(公告)号：US07417281B2

    公开(公告)日：2008-08-26

    申请号：US11733488

    申请日：2007-04-10

    申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

    发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

    IPC分类号： H01L29/94

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

    摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

    摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

    Fabrication method of a nonvolatile semiconductor memory
    74.
    发明授权
    Fabrication method of a nonvolatile semiconductor memory 有权
    非易失性半导体存储器的制造方法

    公开(公告)号：US07141474B2

    公开(公告)日：2006-11-28

    申请号：US11008531

    申请日：2004-12-10

    申请人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

    发明人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

    摘要： A method of fabricating a nonvolatile semiconductor memory including the steps of: sequentially forming a gate insulating layer and a first conductive layer of a floating gate on a semiconductor substrate; depositing an inter-gate insulating layer; forming an opening in a part of the inter-gate insulating layer; depositing a control gate electrode on the inter-gate insulating layer and an exposed portion of the first conductive layer by the opening; and forming the gate electrodes of the memory cell transistors and the gate electrodes of the select transistors by utilizing the etching processes of the control gate electrode, the inter-gate insulating layer and the first conductive layer, wherein the select transistors include at least a part of the exposed portion of the first conductive layer.

    摘要翻译： 一种制造非易失性半导体存储器的方法，包括以下步骤：在半导体衬底上依次形成栅极绝缘层和浮置栅极的第一导电层; 沉积栅极间绝缘层; 在所述栅极绝缘层的一部分中形成开口; 通过所述开口在所述栅极间绝缘层上沉积控制栅极电极和所述第一导电层的暴露部分; 以及通过利用所述控制栅电极，所述栅极间绝缘层和所述第一导电层的蚀刻工艺，形成所述存储单元晶体管的栅电极和所述选择晶体管的栅电极，其中所述选择晶体管至少包括一部分 的第一导电层的暴露部分。

    Nonvolatile semiconductor memory device having element isolating region of trench type
    79.
    发明申请
    Nonvolatile semiconductor memory device having element isolating region of trench type 有权
    具有沟槽型元件隔离区域的非易失性半导体存储器件

    公开(公告)号：US20050236661A1

    公开(公告)日：2005-10-27

    申请号：US11168410

    申请日：2005-06-29

    申请人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    发明人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    IPC分类号： H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

    摘要： A semiconductor device of a selective gate region having a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating film, and an element isolating region including an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer. The element isolating region isolates an element region and is self-aligned with the first electrode layer, a second insulating film is formed on the first electrode layer and the element isolating region, and an open portion exposes a surface of the first electrode layer and is formed in the second insulating film. A second electrode layer is formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.

    摘要翻译： 具有半导体层的选择性栅极区域的半导体器件，形成在半导体层上的第一绝缘膜，形成在第一绝缘膜上的第一电极层，以及包括元件隔离绝缘膜的元件隔离区域，所述元件隔离绝缘膜形成为延伸穿过 第一电极层和第一绝缘膜到达半导体层的内部区域。 元件隔离区域隔离元件区域并且与第一电极层自对准，第二绝缘膜形成在第一电极层和元件隔离区域上，开放部分露出第一电极层的表面，并且是 形成在第二绝缘膜中。 第二电极层形成在第二绝缘膜和第一电极层的暴露表面上，第二电极层经由开口部分电连接到第一电极层。