公开(公告)号：US11914499B2

公开(公告)日：2024-02-27

申请号：US17515212

申请日：2021-10-29

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant ,  Misaele Marletti ,  Alessandro Daolio

IPC: G06F11/36 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3636 ,  G06F11/3082 ,  G06F11/3466

Abstract: A trace-data preparation circuit including a filtering circuit to receive traced memory-write data and a First In First Out buffer coupled with the filtering circuit to receive selected memory-write data filtered by the filtering circuit. The trace-data preparation circuit further including a data compression circuit to provide packaging data to a packaging circuit that groups the selected memory-write data.

公开(公告)号：US20240048405A1

公开(公告)日：2024-02-08

申请号：US18489590

申请日：2023-10-18

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics Design & Application S.R.O.

Inventor： Vaclav Dvorak ,  Fred Rennig

IPC: H04L12/40 ,  G06F13/42

CPC classification number: H04L12/40013 ,  G06F13/423 ,  H04L12/40169 ,  H04L2012/40215

Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

公开(公告)号：US20240048404A1

公开(公告)日：2024-02-08

申请号：US18350345

申请日：2023-07-11

Applicant: STMicroelectronics Application GMBH

Inventor： Fred Rennig

IPC: H04L12/40

CPC classification number: H04L12/40006 ,  H04L2012/40215

Abstract: An electronic device includes a CAN protocol controller, a first communication port configured to be coupled to a first segment of a differential bus, and a second communication port configured to be coupled to a second segment of the differential bus. A first CAN transceiver circuit is coupled to the CAN protocol controller and is configured to receive a first CAN transmission signal and to transmit a first CAN reception signal. The first CAN transceiver is configured to drive a differential voltage at the first segment of the differential bus based on the first CAN transmission signal and to sense a differential voltage at the first segment of the differential bus. The second communication port is enabled in response to a control signal being de-asserted and disabled in response to the control signal being asserted.

公开(公告)号：US11824681B2

公开(公告)日：2023-11-21

申请号：US17814113

申请日：2022-07-21

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Vaclav Dvorak ,  Fred Rennig

IPC: H04L12/40 ,  G06F13/42

CPC classification number: H04L12/40013 ,  G06F13/423 ,  H04L12/40169 ,  H04L2012/40215

Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

公开(公告)号：US11810911B2

公开(公告)日：2023-11-07

申请号：US16897205

申请日：2020-06-09

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMICROELECTRONICS (TOURS) SAS

Inventor： Mathieu Rouviere ,  Arnaud Yvon ,  Mohamed Saadna ,  Vladimir Scarpa

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/872

CPC classification number: H01L27/0629 ,  H01L21/0254 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/40 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/872

Abstract: A monolithic component includes a field-effect power transistor and at least one first Schottky diode inside and on top of a gallium nitride substrate.

公开(公告)号：US11762794B2

公开(公告)日：2023-09-19

申请号：US17747800

申请日：2022-05-18

Applicant: STMicroelectronics Application GMBH

Inventor： Rolf Nandlinger ,  Roberto Colombo

IPC: G06F13/28 ,  G06F9/30 ,  G06F9/38 ,  G06F13/42 ,  G06F21/60 ,  G06F21/72

CPC classification number: G06F13/28 ,  G06F9/30105 ,  G06F9/3877 ,  G06F13/4282 ,  G06F21/602 ,  G06F21/72

Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

公开(公告)号：US20230269150A1

公开(公告)日：2023-08-24

申请号：US18309397

申请日：2023-04-28

Applicant: STMicroelectronics Application GMBH

Inventor： Fred Rennig

IPC: H04L43/08

CPC classification number: H04L43/08 ,  H04L12/40

Abstract: In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.

公开(公告)号：US20230170006A1

公开(公告)日：2023-06-01

申请号：US18056803

申请日：2022-11-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N. V. ,  STMicroelectronics Application GMBH

Inventor： Asif Rashid Zargar ,  Nicolas Bernard Grossier ,  Charul Jain ,  Roberto Colombo

IPC: G11C7/24 ,  G11C7/10

CPC classification number: G11C7/24 ,  G11C7/1039 ,  G11C7/1069

Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

公开(公告)号：US20230053564A1

公开(公告)日：2023-02-23

申请号：US17814113

申请日：2022-07-21

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Vaclav Dvorak ,  Fred Rennig

IPC: H04L12/40 ,  G06F13/42

Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

公开(公告)号：US20230027826A1

公开(公告)日：2023-01-26

申请号：US17858782

申请日：2022-07-06

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics International N.V.

Inventor： Vivek Mohan SHARMA ,  Roberto COLOMBO

IPC: H03M13/11 ,  H03M13/00

Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits. For example the safety monitor circuit comprises a test circuit configured to provide modified data bits and/or modified ECC bits to the error detection circuit as a function of connectivity test control signals, whereby the error detection circuit asserts the error signal as a function of the connectivity test control signals. The processing system comprises also a connectivity test control circuit comprising control registers programmable via the microprocessor, wherein the connectivity test control signals are generated as a function of the content of the control registers.