Abstract:
A mobile communication device for providing QoS of packet transmission is provided. The packet transmission from and to the mobile communication device is performed by repeating a predetermined number of interlaces by a predetermined cycle. In the mobile communication device, a wireless module transmits a first sub-packet of a first packet and a first sub-packet of a second packet to a mobile communication network, and receives a response message corresponding to the first sub-packet of the first packet from the mobile communication network, wherein the first sub-packet of the first packet is transmitted in a first interlace prior to a second interlace in which the first sub-packet of the second packet is transmitted. Also, a controller module calculates a plurality of QoS parameters for a second sub-packet of the second packet in response to the response message, prepares the second sub-packet of the second packet with the QoS parameters, and transmits the second sub-packet of the second packet in the second interlace to the mobile communication network via the wireless module.
Abstract:
A service network for handling abnormal interrupts, including tracking area updates, lower layer failures, and guard timer expiries, during an attach procedure with a user equipment is provided. The service network includes a radio access network and a control node. When the radio access network detecting an abnormal interrupt, the control node aborts the attach procedure by sending a detach request message, via the radio access network, to the user equipment.
Abstract:
A control channel encoder that uses a channel structure that efficiently transmits more information bits, yet achieves sufficient detection and false alarm performance. Disclosed embodiments use a fixed encoder packet size, tail-biting convolutional coding, and Cyclical Redundancy Check (CRC). Further disclosed is a control channel decoder using Viterbi Decoding and a circular trellis check.
Abstract:
A mobile communication device for managing the operation status of wireless transmissions and receptions is provided. In the mobile communication device, a wireless module performs the wireless transmissions and receptions. Also, in the mobile communication device, a controller module activates the wireless module to transmit a scheduling request message to the service network, and keeps the wireless module activated for the wireless receptions in a first predetermined period of time subsequent to the transmission of the scheduling request message.
Abstract:
A first communication device wirelessly coupled to a second communication device. The first communication device includes a first receiver, a message processor, and a first transmitter. The first receiver is configured to receive first signals corresponding to a first number of communication devices, where the second communication device is one of the communication devices, and is also configured to measure first strengths of the first signals. The message processor is configured to determine that a second number of the communication devices can be processed by the first communication device according to the first strengths measured. The first transmitter is configured to transmit one or more first messages to the second communication device indicating the second number.
Abstract:
A communication device wirelessly coupled to another communication device. The communication device includes a first transmitter and a first receiver. The first transmitter is configured to transmit first power control bit information to the base station over a reverse link. The first transmitter has a timeline manager, configured to transmit the first power control bit information at a first rate according to a first pattern within a frame. The first receiver is configured to receive second power control bit information from the another communication device over a forward link. The first receiver has an adaptive controller, configured to determine the first rate and the first pattern. The first rate and the first pattern are selected from a plurality of rates and patterns available for transmission of the first power control bit information and the second power control bit information.
Abstract:
Systems and methods for generating check node updates in the decoding of low-density parity-check (LDPC) codes use new approximations in order to reduce the complexity of implementing a LDPC decoder, while maintaining accuracy. The new approximations approximate the standard float-point sum-product algorithm (SPA), and can reduce the approximation error of min-sum algorithm (MSA) and have almost the same performance under 5 bits fix-point realization as the float-point sum-product algorithm (SPA).
Abstract:
A method for determining slotted mode operation timing in a hybrid access terminal comprises acquiring a first network, determining a first access interval for the first network, acquiring a second network, determining a second access interval for the second network, determining if the first and second access intervals overlap, and re-determining the second access interval when it is determined that the first and second access intervals overlap.
Abstract:
A system for sending multimedia information from at least one base station to one or more mobile stations via at least one wireless communication link includes at least one multimedia source for generating the multimedia information. At least one processor is coupled to the multimedia source for generating a number of data streams derived from the multimedia information on a media control access (MAC) layer. At least one data channel modulator is coupled to the processor for mapping the data streams into a number of data packets on a forward packet data channel between the base station and the mobile station, using a physical layer signaling based on a code-division multiple access (CDMA) or orthogonal frequency division modulation (OFDM) technology.
Abstract:
The present invention concerns an apparatus comprising a memory, a logic circuit and a multiplexer. The memory generally comprises a first address space configured as read only and a second address space configured as read and write. The memory returns a first data item in response to a first address within the first address space. The logic circuit may be configured to (i) deassert a command signal in response to the first address not matching any of a plurality of predetermined addresses and (ii) generate a first branch instruction and assert the command signal in response to the first address matching one of the predetermined addresses in response to the matching. The multiplexer may be configured to select the first data item from the memory or the first branch instruction from the logic circuit in response to the command signal.