利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

3410 records (took 0.04 seconds)

    Demultiplexer gate driver circuit and display panel
    73.
    发明授权
    Demultiplexer gate driver circuit and display panel 有权

    公开(公告)号：US11694587B2

    公开(公告)日：2023-07-04

    申请号：US17057676

    申请日：2020-09-25

    Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

    Inventor： Dian Zhang ,  Ronglei Dai

    IPC: G09G3/20

    CPC classification number: G09G3/20 ,  G09G2300/0408 ,  G09G2300/0804 ,  G09G2300/0809 ,  G09G2310/0267 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2320/0257

    Abstract: A demultiplexer gate driver circuit and a display panel are provided. The demultiplexer gate driver circuit aims at the problem that the output amplitude of the m sub-gate drive signals divided from the gate drive signal by the demultiplexer module is low, which results in a poorer All Gate On function, when the GOA circuit of the demultiplexer module is used to achieve the All Gate On function. The full-on control module is improved by connecting the full-on control module to the m sub-gate drive signals divided from the gate drive signal. The m sub-gate drive signals are directly controlled by the full-on control module to output the high potential at the same time, and there is only one threshold voltage consumption from the full-on control signal to the sub-gate drive signals. The effect of the All Gate On function is effectively improved.

    DISPLAY PANEL AND DISPLAY DEVICE
    74.
    发明公开
    DISPLAY PANEL AND DISPLAY DEVICE 审中-公开

    公开(公告)号：US20230178047A1

    公开(公告)日：2023-06-08

    申请号：US16968372

    申请日：2020-07-03

    Applicant: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

    Inventor： Jue XIONG ,  Bangyin PENG ,  Ilgon KIM

    IPC: G09G3/36

    CPC classification number: G09G3/3677 ,  G09G2300/0408

    Abstract: A display panel of the present application is disclosed. The display panel includes a GOA circuit, a plurality of clock main lines on a side of the GOA circuit, and a plurality of clock branch lines connected to each of the corresponding clock main lines, respectively. By providing the different first protrusion components and second protrusion components in the corresponding clock branch lines, the equivalent impedance of these clock branch lines can be adjusted to be equal. By providing the bridge components with different areas in the corresponding clock branch lines, the equivalent capacitive reactance of these clock branch lines can be adjusted to be equal.

    ARRAY SUBSTRATE AND DISPLAY DEVICE
    77.
    发明公开
    ARRAY SUBSTRATE AND DISPLAY DEVICE 审中-公开

    公开(公告)号：US20230162646A1

    公开(公告)日：2023-05-25

    申请号：US17638836

    申请日：2021-02-04

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Long HAN ,  Libin LIU ,  Lujiang HUANGFU

    IPC: G09G3/20 ,  G09G3/3233

    CPC classification number: G09G3/2074 ,  G09G3/3233 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2300/0465 ,  G09G2300/0819 ,  G09G2310/08 ,  G09G2310/0202 ,  G09G2320/066

    Abstract: The present disclosure relates to an array substrate and a display device. The array substrate includes a plurality of initialization signal lines and a plurality of connection lines. The initialization signal lines are arranged in a conductive layer, extend along a first direction and are arranged at intervals along a second direction, and are used to provide initialization signals to the sub-pixels. The connection lines are arranged in another conductive layer, extend along the second direction and are arranged at intervals along the first direction. Projections of at least one initialization signal line and at least one connection line on the base substrate intersect, and the at least one initialization signal line and the at least one connection line are connected through a via hole, so that the projections of the initialization signal lines and the connection lines on the substrate form a grid-like structure.

    GOA CIRCUIT AND DISPLAY PANEL
    78.
    发明公开
    GOA CIRCUIT AND DISPLAY PANEL 审中-公开

    公开(公告)号：US20230154428A1

    公开(公告)日：2023-05-18

    申请号：US17050205

    申请日：2020-05-26

    Applicant: TCL CHINA CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

    Inventor： Xiaowen Lv

    IPC: G09G3/36 ,  G09G3/3266

    CPC classification number: G09G3/3677 ,  G09G3/3266 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2310/061

    Abstract: A GOA circuit and a display panel are provided. The GOA circuit includes a plurality of GOA units connected in series. Each GOA unit includes a pull-up control module, a pull-up module, a download module, a pull-down maintaining module, a pull-down module, and a bootstrap capacitor. An AC signal applied to the pull-up module has high and low voltage levels. The high voltage level of the AC signal could reduce the rising time and the falling time of the conventional clock signal such that the output of the scan signal could be better. The low voltage level of the AC signal could pull down the signal in the blank time to perform a stress recovery such that the threshold voltage shift of the transistor caused by the high voltage level stress is reduced. This could raise the stability and the lifetime of the circuit.

    GOA UNIT CIRCUIT, DRIVING METHOD, GOA CIRCUIT, AND DISPLAY APPARATUS
    79.
    发明公开
    GOA UNIT CIRCUIT, DRIVING METHOD, GOA CIRCUIT, AND DISPLAY APPARATUS 审中-公开

    公开(公告)号：US20230142651A1

    公开(公告)日：2023-05-11

    申请号：US16958822

    申请日：2019-09-17

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Lubin Shi ,  Ke Meng

    IPC: G09G3/3266

    CPC classification number: G09G3/3266 ,  G09G2300/0408 ,  G09G2310/08 ,  G09G2330/021

    Abstract: A GOA unit circuit is provided with an input sub-circuit configured to set a turn-on voltage to a first node and a turn-off voltage to a second node in response to an input signal and a first clock signal; a first pull-down sub-circuit, a pull-up sub-circuit, a first control sub-circuit, and a second control sub-circuit configured to set voltage levels of the first, the second, and a third nodes. The gate on array unit circuit also includes a first output sub-circuit to output a first output signal at the turn-on voltage triggered by a second clock in response to voltage levels at the first, second nodes and a second output sub-circuit to output a second output signal falling to the turn-off voltage triggered by the first clock and rising to the turn-on voltage triggered by the third clock in response to voltage levels at the first, third nodes.

Patent Agency Ranking