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98 条记录 (耗时 0.012 秒)

    Method to decrease locktime in a phase locked loop
    76.
    发明授权
    Method to decrease locktime in a phase locked loop 有权
    减少锁相环锁定时间的方法

    公开(公告)号：US08503597B2

    公开(公告)日：2013-08-06

    申请号：US12982854

    申请日：2010-12-30

    申请人： Dennis M. Fischette ,  Rohit Kumar

    发明人： Dennis M. Fischette ,  Rohit Kumar

    IPC分类号： H03D3/24

    CPC分类号： H03D3/24 ,  H03L7/1075 ,  H03L2207/06

    摘要： A method and mechanism for reducing lock time of a dual-path phase lock loop (PLL). The PLL comprises a dual-path low-pass filter (LPF). The LPF includes a first filter and a second filter. The first filter comprises a passive second-order lead-lag low-pass filter. The second filter comprises a first-order lag low-pass filter. During a lock-acquisition state, an impedance value within the second stage is bypassed, which increases the loop bandwidth of the PLL. In addition, a resistance within the first stage is increased in order to increase the gain of the first stage and maintain stability within the PLL. During a lock state, the impedance value may no longer be bypassed and the increased resistance may be returned to its original value.

    摘要翻译： 一种减少双路锁相环（PLL）锁定时间的方法和机制。 PLL包括双通道低通滤波器（LPF）。 LPF包括第一过滤器和第二过滤器。 第一滤波器包括无源二阶超前延迟低通滤波器。 第二滤波器包括一阶滞后低通滤波器。 在锁定获取状态期间，旁路第二级中的阻抗值，这增加了PLL的环路带宽。 此外，增加第一级内的电阻以增加第一级的增益并保持PLL内的稳定性。 在锁定状态期间，阻抗值可能不再被旁路，并且增加的电阻可能返回到其原始值。

    Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection
    77.
    发明授权
    Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection 有权
    用于解调器的复数数字锁相环和最佳系数选择方法

    公开(公告)号：US07826564B2

    公开(公告)日：2010-11-02

    申请号：US12234343

    申请日：2008-09-19

    申请人： Henrik T. Jensen

    发明人： Henrik T. Jensen

    IPC分类号： H03D3/18 ,  H03D3/24

    CPC分类号： H03D3/24 ,  H03D2200/0082

    摘要： A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a controller, which multiplies the phase error by a gain factor selected to stabilize and optimize the phase locked loop and produces an output signal for use in extracting a frequency deviation present in the complex digital input signal. The output signal is also input to a numerically controlled oscillator that tracks the phase of the complex digital input signal based on the output signal and produces the complex digital feedback signal.

    摘要翻译： 用于数字解调器的复数数字锁相环包括相位检测器，用于产生指示复数数字输入信号和复数数字反馈信号之间的相位差的相位误差。 将相位误差输入到控制器，该控制器将相位误差乘以所选择的增益因子，以稳定和优化锁相环，并产生用于提取复数字输入信号中存在的频率偏差的输出信号。 输出信号也输入到数控振荡器，该振荡器基于输出信号跟踪复数数字输入信号的相位，并产生复数数字反馈信号。

    Synchronous carrier recovery circuit and injection locked oscillator
    78.
    发明授权
    Synchronous carrier recovery circuit and injection locked oscillator 失效
    同步载波恢复电路和注入锁定振荡器

    公开(公告)号：US6133802A

    公开(公告)日：2000-10-17

    申请号：US16275

    申请日：1998-01-30

    申请人： Zhigang Ma

    发明人： Zhigang Ma

    IPC分类号： H03B5/12 ,  H03D3/24 ,  H03K3/354 ,  H03L7/06 ,  H03L7/24 ,  H04L7/027 ,  H04L7/033 ,  H03B5/36 ,  H03D3/00 ,  H03D3/02

    CPC分类号： H03B5/366 ,  H03B5/364 ,  H03D3/24 ,  H03K3/354 ,  H03L7/06 ,  H03L7/0805 ,  H03L7/24 ,  H04L7/027 ,  H04L7/033

    摘要： A simple carrier recovery circuit capable of accurately detecting and synchronizing an incoming carrier frequency without the use of a phase locked loop (PLL) is provided. Instead of a PLL, the carrier recovery circuit includes an injection locked oscillator. The injection locked oscillator includes an input for connection to the received modulated signal. The gain of an inverter stage of a amplifier in the injection locked oscillator is modulated by the received modulated signal using an injection transistor connected between the power source and the output of the inverter stage. The gate of the injection transistor receives a signal corresponding to the received modulated signal.

    摘要翻译： 提供了一种能够在不使用锁相环（PLL）的情况下精确地检测和同步输入载波频率的简单载波恢复电路。 代替PLL，载波恢复电路包括一个注入锁定的振荡器。 注入锁定振荡器包括用于连接到接收的调制信号的输入。 注入锁定振荡器中的放大器的反相器级的增益由连接在电源和反相器级的输出端之间的注入晶体管通过接收的调制信号进行调制。 注入晶体管的栅极接收与接收到的调制信号相对应的信号。

    Fast-acting Costas loop
    79.
    发明授权
    Fast-acting Costas loop 失效

    公开(公告)号：US5956375A

    公开(公告)日：1999-09-21

    申请号：US873253

    申请日：1997-06-11

    申请人： Emmanuel Kanterakis

    发明人： Emmanuel Kanterakis

    IPC分类号： H03D3/00 ,  H03D3/24 ,  H03L7/087 ,  H03L7/107 ,  H04L27/00 ,  H04L27/227 ,  H04L27/14 ,  H04L27/16 ,  H04L27/22

    CPC分类号： H03L7/087 ,  H03D3/007 ,  H03D3/24 ,  H03L7/107 ,  H04L27/2273 ,  H04L2027/0028 ,  H04L2027/0057

    摘要： A system and method using a Costas loop to effect accelerated convergence with minimal system complexity. The system comprises an in-phase-limiter and a quadrature-phase limiter, operatively coupled to an EXCLUSIVE-OR gate, for exclusively-ORing an in-phase-sign signal and a quadrature-phase-sign signal to output a first error signal, responsive to the signals having same signs, or a second error signal, responsive to the signals having different signs. An AGC circuit, operatively coupled to an output of the EXCLUSIVE-OR gate, increases and decreases a voltage level of an AGC signal responsive to two consecutive first or second error signals and consecutive dissimilar error signals, respectively. A voltage-controlled oscillator, operatively coupled to an output of the AGC circuit and responsive to the increased or decreased voltage level, changes the frequency of a voltage-controlled-oscillator output signal.

    Fast-acting costas loop
    80.
    发明授权
    Fast-acting costas loop 失效
    快速行动的costas循环

    公开(公告)号：US5640425A

    公开(公告)日：1997-06-17

    申请号：US578422

    申请日：1995-12-26

    申请人： Emmanuel Kanterakis

    发明人： Emmanuel Kanterakis

    IPC分类号： H03D3/00 ,  H03D3/24 ,  H03L7/087 ,  H03L7/107 ,  H04L27/00 ,  H04L27/227 ,  H04L27/14 ,  H04L27/16 ,  H04L27/22

    CPC分类号： H03L7/087 ,  H03D3/007 ,  H03D3/24 ,  H03L7/107 ,  H04L27/2273 ,  H04L2027/0028 ,  H04L2027/0057

    摘要： A system and method using a Costas loop to effect accelerated convergence with minimal system complexity. The system comprises an in-phase-limiter and a quadrature-phase limiter, operatively coupled to an EXCLUSIVE-OR gate, for exclusively-ORing an in-phase-sign signal and a quadrature-phase-sign signal to output a first error signal, responsive to the signals having same signs, or a second error signal, responsive to the signals having different signs. An AGC circuit, operatively coupled to an output of the EXCLUSIVE-OR gate, increases and decreases a voltage level of an AGC signal responsive to two consecutive first or second error signals and consecutive dissimilar error signals, respectively. A voltage-controlled oscillator, operatively coupled to an output of the AGC circuit and responsive to the increased or decreased voltage level, changes the frequency of a voltage-controlled-oscillator output signal.

    摘要翻译： 使用Costas循环的系统和方法以最小的系统复杂度实现加速收敛。 该系统包括可操作地耦合到异或门的同相限幅器和正交限幅器，用于对同相符号信号和正交相位信号进行异或运算以输出第一误差信号 响应于具有相同符号的信号或响应于具有不同符号的信号的第二误差信号。 可操作地耦合到异或门的输出的AGC电路分别响应于两个连续的第一或第二误差信号和连续的不相似的误差信号而增加和减小AGC信号的电压电平。 电压控制振荡器可操作地耦合到AGC电路的输出并且响应于增加或降低的电压电平来改变压控振荡器输出信号的频率。