公开(公告)号：US08860511B2

公开(公告)日：2014-10-14

申请号：US13671938

申请日：2012-11-08

申请人： Semiconductor Technology Academic Research Center

发明人： Kenichi Okada ,  Ahmed Magdi Hassan Musa

IPC分类号： H03L7/00 ,  H03L5/00 ,  H03L7/183 ,  H03L7/24 ,  H03B19/06

CPC分类号： H03L5/00 ,  H03B19/06 ,  H03K3/0322 ,  H03L7/183 ,  H03L7/24

摘要： A frequency divider of an injection locked type capable of division by 2, division by 4, and further division by 8 with a simpler configuration is disclosed and the frequency divider includes a ring oscillator including M (M is an even number) delay elements, the tails of two delay elements M/2 delay elements apart from each other are connected to a differential pair and transistors, to the gates of which the input oscillation signal is applied, are connected to the differential pair, and the differential pair is caused to generate a differential signal of the input oscillation signal, which is a divide-by-2 signal of the input oscillation signal, and when dividing the frequency of the input oscillation signal by 8, the portion of the differential pair to be connected to the tail of the delay element is caused to have a two-stage configuration, which is a vertically stacked configuration.

摘要翻译： 公开了一种注入锁定型的分频器，其能够除以2，除以4，并且以更简单的配置进一步除以8，并且分频器包括包括M（M是偶数）延迟元件的环形振荡器， 两个延迟元件M / 2延迟元件相互分离的尾部连接到差分对，并且施加输入振荡信号的栅极的晶体管连接到差分对，并且使差分对产生 作为输入振荡信号的2分频信号的输入振荡信号的差分信号，当将输入振荡信号的频率除以8时，将要连接到尾部的差分对的部分 使延迟元件具有两级配置，其是垂直堆叠的配置。

公开(公告)号：US08803725B2

公开(公告)日：2014-08-12

申请号：US13862723

申请日：2013-04-15

申请人： Semiconductor Technology Academic Research Center

发明人： Yuji Osaki ,  Tetsuya Hirose

IPC分类号： H03M1/34

CPC分类号： H03M1/34 ,  H03M1/1014 ,  H03M1/56

摘要： A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value.

摘要翻译： 单斜率AD转换器电路包括一个比较器，用于将经过时间的预定斜率随斜率变化的斜坡电压与模拟输入电压进行比较，计数器与比较器的比较处理并行地计数预定时钟;以及控制器，其输出 作为AD转换的第一数字值，与斜坡电压小于模拟输入电压的经过时间对应的时钟计数值。 比较器将斜坡电压与预定的第一参考电压进行比较，计数器与比较过程并行计数时钟，并且控制器将与经过的时间相对应的时钟计数值作​​为AD转换的第二数字值输出。

公开(公告)号：US20140021987A1

公开(公告)日：2014-01-23

申请号：US14008961

申请日：2012-03-12

申请人： Kenichi Okada

发明人： Kenichi Okada

IPC分类号： H03L7/083

CPC分类号： H03L7/083 ,  H03L7/24 ,  H03L2207/06

摘要： Provided is an injection-locked-type frequency-locked oscillator capable of stable operation and exhibiting low phase noise. This injection-locked-type frequency-locked oscillator comprises: a locked loop (10) provided with a first injection-locked-type signal-controlled oscillator (14); and a second injection-locked-type signal-controlled oscillator (20). In the first injection-locked-type signal-controlled oscillator (14), an output frequency signal is made variable by an oscillation frequency control signal, and no reference clock signal is injected. In the second injection-locked-type signal-controlled oscillator (20), a reference clock signal corresponding to a reference clock signal of the locked loop (10) is injected, an oscillation frequency control signal corresponding to the same oscillation frequency control signal as the oscillation frequency control signal to the first injection-locked-type signal-controlled oscillation (14) is inputted, the circuit configuration is the same as that of the first injection-locked-type signal-controlled oscillator, and a desired frequency signal is outputted.

摘要翻译： 提供了一种能够稳定运行并且表现出低相位噪声的注入锁定型锁频振荡器。 该注入锁定型锁频振荡器包括：具有第一注入锁定型信号控制振荡器（14）的锁定环（10）; 和第二注入锁定型信号控制振荡器（20）。 在第一注入锁定型信号控制振荡器（14）中，通过振荡频率控制信号使输出频率信号变化，并且不注入参考时钟信号。 在第二注入锁定型信号控制振荡器（20）中，注入与锁定环路（10）的参考时钟信号相对应的基准时钟信号，对应于相同振荡频率控制信号的振荡频率控制信号， 输入到第一注入锁定型信号控制振荡（14）的振荡频率控制信号，该电路配置与第一注入锁定型信号控制振荡器相同，所需频率信号为 输出。

公开(公告)号：US08519880B2

公开(公告)日：2013-08-27

申请号：US13470605

申请日：2012-05-14

申请人： Hiroshi Kawaguchi ,  Masahiko Yoshimoto ,  Toshihiro Konishi ,  Shintaro Izumi

发明人： Hiroshi Kawaguchi ,  Masahiko Yoshimoto ,  Toshihiro Konishi ,  Shintaro Izumi

IPC分类号： H03M1/50

CPC分类号： H03M1/50 ,  H03M3/416

摘要： An AD converter includes a VT converter circuit part which inputs an analog input voltage and a sampling clock, converts the analog input voltage to a corresponding delay time, and outputs time domain data. A ring oscillator circuit part of N stages inputs the time domain data, and an error propagation circuit part takes out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagate the delay information to the ring oscillator circuit part of a subsequent stage. A counter circuit part measures a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage, and an output signal generator part generates an output signal from an output counted value of each counter circuit part. A reset part resets each error propagation circuit part and each counter circuit part with a sampling clock.

摘要翻译： AD转换器包括输入模拟输入电压和采样时钟的VT转换器电路部分，将模拟输入电压转换为相应的延迟时间，并输出时域数据。 N级的环形振荡器电路部分输入时域数据，误差传播电路部分从前级的环形振荡电路部分的相位信息中取出包含量化误差的延迟信息，并将延迟信息传播到环 振荡电路是后续阶段的一部分。 计数器电路部分测量每个级的环形振荡器电路部分的输出振荡波形的波数，并且输出信号发生器部分根据每个计数器电路部分的输出计数值产生输出信号。 复位部分将采样时钟复位每个误差传播电路部分和每个计数器电路部分。

公开(公告)号：US20130120073A1

公开(公告)日：2013-05-16

申请号：US13671938

申请日：2012-11-08

申请人： Semiconductor Technology Academic Research C

发明人： Kenichi OKADA ,  Ahmed Magdi Hassan MUSA

IPC分类号： H03L5/00

CPC分类号： H03L5/00 ,  H03B19/06 ,  H03K3/0322 ,  H03L7/183 ,  H03L7/24

摘要： A frequency divider of an injection locked type capable of division by 2, division by 4, and further division by 8 with a simpler configuration is disclosed and the frequency divider includes a ring oscillator including M (M is an even number) delay elements, the tails of two delay elements M/2 delay elements apart from each other are connected to a differential pair and transistors, to the gates of which the input oscillation signal is applied, are connected to the differential pair, and the differential pair is caused to generate a differential signal of the input oscillation signal, which is a divide-by-2 signal of the input oscillation signal, and when dividing the frequency of the input oscillation signal by 8, the portion of the differential pair to be connected to the tail of the delay element is caused to have a two-stage configuration, which is a vertically stacked configuration.

摘要翻译： 公开了一种注入锁定型的分频器，其能够除以2，除以4，并且以更简单的配置进一步除以8，并且分频器包括包括M（M是偶数）延迟元件的环形振荡器， 两个延迟元件M / 2延迟元件相互分离的尾部连接到差分对，并且施加输入振荡信号的栅极的晶体管连接到差分对，并且使差分对产生 作为输入振荡信号的2分频信号的输入振荡信号的差分信号，当将输入振荡信号的频率除以8时，将要连接到尾部的差分对的部分 使延迟元件具有两级配置，其是垂直堆叠的配置。

公开(公告)号：US08330499B2

公开(公告)日：2012-12-11

申请号：US13036405

申请日：2011-02-28

申请人： Tetsuya Hirose ,  Keishi Tsubaki ,  Masahiro Numa

发明人： Tetsuya Hirose ,  Keishi Tsubaki ,  Masahiro Numa

IPC分类号： H03K5/22

CPC分类号： H03K5/2481

摘要： In a comparator circuit having a differential amplifier, which makes a logical judgment by comparing an input voltage with a reference voltage, generates and outputs a resulting output voltage thereof, a current source generates and supplies a bias current of a predetermined minute current to the differential amplifier, and a first inverter circuit inverts a differential voltage from the differential amplifier. An adaptive bias current generator circuit detects the bias current of the current source, and a through current of the first inverter circuit. The adaptive bias current generator circuit generates and supplies an adaptive bias current for executing adaptive bias current control to the differential amplifier to allow the differential amplifier to operate with the bias current upon no logical judgment, and to allow the differential amplifier to operate by using the adaptive bias current obtained by increasing the bias current upon logical judgment.

摘要翻译： 在具有差分放大器的比较器电路中，其通过将输入电压与参考电压进行比较来进行逻辑判断，产生并输出其产生的输出电压，电流源产生并将预定的微小电流的偏置电流提供给差分 放大器，并且第一反相器电路将差分放大器的差分电压反相。 自适应偏置电流发生器电路检测电流源的偏置电流和第一反相器电路的通过电流。 自适应偏置电流发生器电路产生并提供用于对差分放大器执行自适应偏置电流控制的自适应偏置电流，以允许差分放大器在无逻辑判断时与偏置电流一起工作，并且允许差分放大器通过使用 通过逻辑判断增加偏置电流而获得的自适应偏置电流。

公开(公告)号：US08304908B2

公开(公告)日：2012-11-06

申请号：US12382624

申请日：2009-03-19

申请人： Junichi Koike ,  Yoshito Fujii ,  Jun Iijima ,  Noriyoshi Shimizu ,  Kazuyoshi Maekawa ,  Koji Arita ,  Ryotaro Yagi ,  Masaki Yoshimaru

发明人： Junichi Koike ,  Yoshito Fujii ,  Jun Iijima ,  Noriyoshi Shimizu ,  Kazuyoshi Maekawa ,  Koji Arita ,  Ryotaro Yagi ,  Masaki Yoshimaru

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/74

CPC分类号： H01L21/76853 ,  H01L21/288 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76861 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilevel interconnect structure in a semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.

摘要翻译： 半导体器件中的多层互连结构包括形成在半导体晶片上的第一绝缘层，形成在第一绝缘层上的Cu互连层，形成在Cu互连层上的第二绝缘层和形成在界面处的金属氧化物层 在Cu互连层和第二绝缘层之间。 金属氧化物层通过在Cu互连层上浸渍诸如Sn或Zn的金属，然后在氧化气氛中对镀层进行热处理而形成。

公开(公告)号：US08295413B2

公开(公告)日：2012-10-23

申请号：US12622259

申请日：2009-11-19

申请人： Naoto Sasaoka ,  Yoshio Itoh

发明人： Naoto Sasaoka ,  Yoshio Itoh

IPC分类号： H04L27/06

CPC分类号： H04L27/2657 ,  H04B7/01 ,  H04L27/2672 ,  H04L27/2679 ,  H04L27/2695

摘要： A device of an example of the invention comprises a first section of which performs inverse fast Fourier transform for a channel estimation value obtained by channel estimation to obtain a channel impulse response, a second section which selects paths that belong to a group having a large element based on elements of paths for the channel impulse response, a third section which calculates autocorrelation values by time averaging for each of the paths selected by the second section, a fourth section which obtains an ensemble average value of the autocorrelation values by time averaging obtained by the third section, and a fifth section which obtains a Doppler frequency associated with the ensemble average value based on a characteristic of a relationship between an autocorrelation value and a Doppler frequency and the ensemble average value.

摘要翻译： 本发明的一个实施例的装置包括：第一部分对通过信道估计获得的信道估计值进行快速傅立叶逆变换以获得信道脉冲响应;第二部分，选择属于具有大元素的组的路径 基于用于信道脉冲响应的路径的元素，第三部分，其通过对由第二部分选择的每个路径进行时间平均来计算自相关值;第四部分，通过时间平均获得自相关值的整体平均值， 第三部分和第五部分，其基于自相关值和多普勒频率与整体平均值之间的关系的特性来获得与整体平均值相关联的多普勒频率。

公开(公告)号：US08244788B2

公开(公告)日：2012-08-14

申请号：US11289695

申请日：2005-11-30

申请人： Masatoshi Ishikawa ,  Idaku Ishii ,  Takashi Komuro ,  Shingo Kagami

发明人： Masatoshi Ishikawa ,  Idaku Ishii ,  Takashi Komuro ,  Shingo Kagami

IPC分类号： G06F7/38

CPC分类号： G01J1/4228 ,  G01J1/0204 ,  H04N5/335

摘要： A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.

摘要翻译： 具有容纳在单个半导体芯片上的多个处理元件的半导体集成电路器件具有锁存电路和选择电路。 锁存电路设置在每个处理元件的输出处。 选择电路从由上，下，左，右处理元件组成的组和零信号中选择输入源。

公开(公告)号：US08149067B2

公开(公告)日：2012-04-03

申请号：US12782519

申请日：2010-05-18

申请人： Kenichi Okada

发明人： Kenichi Okada

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/1243

摘要： A voltage-controlled oscillator that can achieve low phase noise while ensuring stable oscillation startup and stable oscillation maintenance even under low supply voltage conditions. The voltage-controlled oscillator includes an LC parallel resonant circuit, whose impedance varies with a control input voltage and a negative resistance circuit for introducing negative resistance into the LC parallel resonant circuit, wherein the negative resistance circuit includes at least: a first amplifier circuit, provided in parallel with the LC parallel resonant circuit and having a first pair of transistors cross-coupled via a capacitor, that achieves class-C amplifier operation by biasing the gate of each transistor in the first transistor pair with a first bias voltage; and a similarly configured second amplifier circuit that achieves class-C amplifier operation by biasing the gate of each transistor with a second bias voltage which is different from the first bias voltage.

摘要翻译： 一个压控振荡器，即使在低电源条件下，也能确保稳定的振荡启动和稳定的振荡维护，从而实现低相位噪声。 压控振荡器包括LC并联谐振电路，其阻抗随着控制输入电压而变化，负电阻电路用于将负电阻引入LC并联谐振电路，其中负电阻电路至少包括：第一放大电路， 提供与LC并联谐振电路并联并且具有通过电容器交叉耦合的第一对晶体管，其通过以第一偏置电压偏置第一晶体管对中的每个晶体管的栅极来实现C类放大器的操作; 以及类似配置的第二放大器电路，其通过以与第一偏置电压不同的第二偏置电压来偏置每个晶体管的栅极来实现C类放大器的操作。