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1.发明申请SEMICONDUCTOR DEVICE, STORAGE DEVICE, AND CONTROL METHOD OF STORAGE DEVICE 审中-公开半导体器件，存储器件和存储器件的控制方法公开(公告)号：US20150221364A1
公开(公告)日：2015-08-06
申请号：US14608674
申请日：2015-01-29
发明人： Toshiro HIRAMOTO
IPC分类号： G11C11/419 , G11C5/06
CPC分类号： G11C11/419
摘要： A semiconductor device includes a plurality of storage elements each having a plurality of MOS transistors forming a latch circuit, a stored data setting unit configured to write inverted data of nonvolatile data that is read when each of the plurality of storage elements functions as a nonvolatile memory cell to each of the plurality of storage elements, and a voltage application unit configured to store the nonvolatile data in each of the plurality of storage elements by applying a predetermined high voltage higher than a power source voltage applied during normal latch operation to each of the latch circuits.
摘要翻译： 半导体器件包括多个存储元件，每个存储元件具有形成锁存电路的多个MOS晶体管;存储数据设置单元，被配置为写入当多个存储元件中的每一个用作非易失性存储器时被读取的非易失性数据的反相数据 多个存储元件中的每一个的单元，以及电压施加单元，被配置为通过施加比在正常锁存操作期间施加的电源电压高的预定高电压来将多个非易失性数据存储在多个存储元件的每一个中 锁存电路。
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2.发明授权Differential amplifier circuit with ultralow power consumption provided with adaptive bias current generator circuit 有权带有自适应偏置电流发生器电路的超低功耗差分放大电路公开(公告)号：US08896378B2
公开(公告)日：2014-11-25
申请号：US13752919
申请日：2013-01-29
发明人： Tetsuya Hirose , Yuji Osaki , Yumiko Tsuruya , Osamu Kobayashi
CPC分类号： H03F3/45179 , H03F1/0261 , H03F3/3028 , H03F3/45183 , H03F2203/30021 , H03F2203/45244 , H03F2203/45454 , H03F2203/45626
摘要： A differential amplifier circuit includes a differential operational amplifier that includes a differential pair circuit and operates based on a constant bias current supplied from a bias current source circuit, and the differential amplifier circuit includes a bias current generator circuit. A current monitor circuit detects two currents flowing through the differential pair circuit in correspondence with differential input voltages inputted to the differential pair circuit, and detects a minimum current of the two currents for a difference voltage of the differential input voltages as a monitored current. A current comparator circuit compares the monitored current with the constant bias current. A current amplifier circuit amplifies a voltage corresponding to the comparison result, and controls currents flowing through the differential pair circuit based on an amplified voltage, and the bias current generator circuit performs negative feedback adaptive control such that the bias current increases as the monitored current decreases.
摘要翻译： 差分放大器电路包括差分运算放大器，其包括差分对电路，并且基于从偏置电流源电路提供的恒定偏置电流进行操作，并且差分放大器电路包括偏置电流发生器电路。 电流监视电路对应于输入到差分对电路的差分输入电压检测流过差分对电路的两个电流，并且将差分输入电压的差分电压的两个电流的最小电流检测为监视电流。 电流比较器电路将监控的电流与恒定偏置电流进行比较。 电流放大器电路放大对应于比较结果的电压，并且基于放大的电压控制流过差分对电路的电流，并且偏置电流发生器电路执行负反馈自适应控制，使得偏置电流随监视电流减小而增加 。
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公开(公告)号：US20140219355A1
公开(公告)日：2014-08-07
申请号：US14041965
申请日：2013-09-30
发明人： Satoshi GOTO , Jinjia Zhou , Dajiang Zhou
IPC分类号： H04N7/36
摘要： A motion estimation device that reduces computational complexity while maintaining high prediction performance includes: block search means searching for a reference block that most approximates a prediction target block within a search range in a past direction frame F (−) or in a future direction frame F (+); search center setting means setting a search center in F (−) and F (+); and search range setting means setting a search range around the search center in F (−) and F (+), wherein the search range setting means sets a relatively large or small search range when F (0) is a P frame and switches assignment of large and small search ranges sequentially between two neighboring prediction target blocks, and the search center setting means sets a position identified by a motion vector predictor as a search center for a frame to which the relatively small search range is assigned.
摘要翻译： 一种在维持高预测性能的同时降低计算复杂性的运动估计装置包括：块搜索装置，搜索最近似于过去方向帧F（ - ）或未来方向帧F（ - ）的搜索范围内的预测目标块的参考块 （+）; 搜索中心设置意味着在F（ - ）和F（+）中设置搜索中心; 并且搜索范围设置意味着在F（ - ）和F（+）中设置搜索中心周围的搜索范围，其中当F（0）是P帧时，搜索范围设置装置设置相对较大或小的搜索范围，并切换分配 在两个相邻的预测目标块之间顺序地搜索大小搜索范围，并且搜索中心设置装置将由运动矢量预测器识别的位置设置为分配相对小的搜索范围的帧的搜索中心。
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4.发明申请TD CONVERTER AND AD CONVERTER WITH NO OPERATIONAL AMPLIFIER AND NO SWITCHED CAPACITOR 有权TD转换器和AD转换器，无操作放大器和无开关电容器公开(公告)号：US20130307713A1
公开(公告)日：2013-11-21
申请号：US13874531
申请日：2013-05-01
IPC分类号： H03M1/50
CPC分类号： H03M1/50 , G04F10/005
摘要： A TD converter is provided for digitally converting a delay time value into a digital value. In the TD converter, an oscillator circuit part inputs time domain data. A first-state counter circuit part measures a number of waves of an output oscillation waveform from the oscillator circuit part when time domain data is in a first state, and a second-state counter circuit part measures a number of waves of the output oscillation waveform from the oscillator circuit part when the time domain data is in a second state. An output signal generator part generates an output signal based on output count values of the first-state counter circuit part and the second-state counter circuit part, and a frequency control circuit controls the oscillator circuit part to always oscillate and to control an oscillation frequency of the oscillator circuit part.
摘要翻译： 提供了一种TD转换器，用于将延迟时间值数字转换为数字值。 在TD转换器中，振荡器电路部分输入时域数据。 当时域数据处于第一状态时，第一状态计数器电路部分测量来自振荡器电路部分的输出振荡波形的波数，并且第二状态计数器电路部分测量输出振荡波形的波数 当时域数据处于第二状态时，来自振荡器电路部分。 输出信号发生器部分基于第一状态计数器电路部分和第二状态计数器电路部分的输出计数值产生输出信号，并且频率控制电路控制振荡器电路部分总是振荡并控制振荡频率 的振荡器电路部分。
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5.发明申请Semiconductor integrated circuit device having body biasing circuit for generating forward well bias voltage of suitable level by using simple circuitry 有权具有主体偏置电路的半导体集成电路器件，用于通过使用简单电路产生适当电平的正向阱偏置电压公开(公告)号：US20040014268A1
公开(公告)日：2004-01-22
申请号：US10618710
申请日：2003-07-15
IPC分类号： H01L021/8238
CPC分类号： H01L27/0928 , H01L27/0218 , H01L27/0727 , H01L27/092 , H01L2924/0002 , H03K17/04106 , H03K19/00384 , H03K19/01707 , Y10S257/901 , H01L2924/00
摘要： A semiconductor integrated circuit device has a MISFET and a body biasing circuit. The MISFET has a source electrode and a drain electrode of a first conductivity type and a gate electrode, and the MISFET is formed in a well of a second conductivity type. The body biasing circuit generates a voltage in the well by passing a prescribed current in a forward direction into a diode which is formed from the well and the source electrode of the MISFET.
摘要翻译： 半导体集成电路器件具有MISFET和主体偏置电路。 MISFET具有第一导电类型的源电极和漏电极和栅电极，并且MISFET形成在第二导电类型的阱中。 主体偏置电路通过将正向的规定电流传递到由阱和MISFET的源电极形成的二极管中，在阱中产生电压。
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公开(公告)号：US20030229485A1
公开(公告)日：2003-12-11
申请号：US10350127
申请日：2003-01-24
IPC分类号： G06F009/455
CPC分类号： G06F9/455 , G06F9/4494
摘要： An emulation system for data-driven processors which aims at shortening the emulation time by employing parallel processing techniques without increasing overhead. The emulation system emulates virtual data-driven processors by using real data-driven processors. The emulation is performed by dividing the functionality of the processor into a data path and a timing path. In the data path emulation, each virtual packet to be processed in the virtual processor is expressed as a PACKET message, and the processing operation of the virtual packet is evaluated for each functional block. In the timing path emulation, a SEND signal and an ACK signal, to be controlled by a self-timed transfer control mechanism and a gate logic, are expressed as a SEND message and an ACK message, respectively, and stage-to-stage transfer operations of the SEND signal and the ACK signal are evaluated.
摘要翻译： 一种用于数据驱动处理器的仿真系统，旨在通过采用并行处理技术来缩短仿真时间，而不会增加开销。 仿真系统通过使用真正的数据驱动处理器来模拟虚拟数据驱动处理器。 通过将处理器的功能划分为数据路径和定时路径来执行仿真。 在数据路径仿真中，在虚拟处理器中要处理的每个虚拟分组被表示为PACKET消息，并且为每个功能块评估虚拟分组的处理操作。 在定时路径仿真中，要由自定时传输控制机制和门逻辑控制的SEND信号和ACK信号分别表示为SEND消息和ACK消息，并且分阶段传送 评估SEND信号和ACK信号的操作。
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7.发明申请Semiconductor integrated circuit device having a plurality of photo detectors and processing elements 失效具有多个光电检测器和处理元件的半导体集成电路器件公开(公告)号：US20030141434A1
公开(公告)日：2003-07-31
申请号：US10200332
申请日：2002-07-23
发明人： Masatoshi Ishikawa , Idaku Ishii , Takashi Komuro , Shingo Kagami
IPC分类号： H01L027/00
CPC分类号： G01J1/4228 , G01J1/0204 , H04N5/335
摘要： A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.
摘要翻译： 具有容纳在单个半导体芯片上的多个处理元件的半导体集成电路器件具有锁存电路和选择电路。 锁存电路设置在每个处理元件的输出处。 选择电路从由上，下，左，右处理元件组成的组和零信号中选择输入源。
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公开(公告)号：US20030071603A1
公开(公告)日：2003-04-17
申请号：US10176063
申请日：2002-06-21
发明人： Takahide Sato , Nobuo Fujii , Sigetaka Takagi , Kazuyuki Wada
IPC分类号： G05F003/16
摘要： A voltage-to-current conversion circuit composed of MOSFETs of the same polarity and an OTA with Rail-to-Rail with a simple configuration that uses the same have been disclosed. The voltage-to-current conversion circuit comprises a first MOSFET, to which a fixed drain-source voltage is applied all the time, and which generates a first current signal for an input voltage, a second MOSFET, which has the same polarity as that of the first MOSFET, to which the fixed drain-source voltage is applied all the time, and which generates a second current signal complementary to the first current signal for the input voltage, and a difference current operation circuit that performs the operation of subtraction between the first current signal and the second current signal, thereby an output current is generated in accordance with the input voltage.
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9.发明申请Process variable identification method, process variable identification apparatus, and evaluation sample 审中-公开过程变量识别方法，过程变量识别装置和评估样本公开(公告)号：US20030055618A1
公开(公告)日：2003-03-20
申请号：US10247440
申请日：2002-09-18
发明人： Hiroo Masuda
IPC分类号： G06F017/10
CPC分类号： G06F17/5036
摘要： The present invention includes calculating an inter-wiring capacitance from process variables including a structural variable and a material constant of each interlayer insulating film in a multi-wiring structural including a first wiring layer, a second wiring layer having a pluraltiy of pitch wirings with a width W arranged at a pitch P, a third wiring layer and a pluraltiy of interlayer insulating films which insulate and separate the first to third wiring layers from each other, modeling a function expression in which the process variables are determined as variables and the inter-wiring capacitance is determiend as a response variable from the relationship between the obtained inter-wiring capacitance and the process variables, creating actual multi-layer wiring structures and measuring an inter-wiring capacitance from each created multi-layer wiring structure, and identifying the process variables of the actually formed multi-layer wiring structure from the measured inter-wiring capacitances based on the modeled function expression.
摘要翻译： 本发明包括在包括第一布线层的多布线结构中的包括每个层间绝缘膜的结构变量和材料常数的工艺变量中计算布线间电容，具有多个间距布线的第二布线层具有 宽度W以间距P布置，第三布线层和多个层间绝缘膜，其将第一至第三布线层彼此绝缘和分离，对其中将过程变量确定为变量的函数表达式进行建模， 根据所获得的布线间电容与工艺变量之间的关系，确定布线电容作为响应变量，产生实际的多层布线结构，并测量每个创建的多层布线结构的布线间电容，以及识别该工艺 实际形成的多层布线结构的变量来自测量的布线 基于模型函数表达式的电容。
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公开(公告)号：US20020131550A1
公开(公告)日：2002-09-19
申请号：US10068104
申请日：2002-02-05
发明人： Hiroshi Fujioka , Masaharu Oshima
IPC分类号： G01T001/36 , G01N023/223
CPC分类号： G01N23/06
摘要： Evaluating electrical properties of a semiconductor device by measuring and analyzing a junction capacitance of a semiconductor provided in the semiconductor device and a transient change of the junction capacitance while applying an X-ray beam to the semiconductor device intermittently, and evaluating a structure and electron states of the semiconductor by measuring and analyzing an energy spectrum of an X-ray beam absorbed into an element present in the semiconductor while applying an X-ray beam to the semiconductor device continuously.
摘要翻译： 通过测量和分析半导体器件中提供的半导体的结电容和间断地向半导体器件施加X射线束的结电容的瞬时变化来评估半导体器件的电特性，并且评估结构和电子状态 通过测量和分析吸收到存在于半导体中的元素的X射线束的能谱，同时将X射线束连续施加到半导体器件。
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