Fault tolerant processor for real-time systems

    公开(公告)号:US10423417B2

    公开(公告)日:2019-09-24

    申请号:US14741738

    申请日:2015-06-17

    申请人: MIPS Tech, LLC

    发明人: Julian Bailey

    IPC分类号: G06F11/00 G06F9/38 G06F11/14

    摘要: A fault tolerant multi-threaded processor uses the temporal and/or spatial separation of instructions running in two or more different threads. An instruction is fetched, decoded and executed by each of two or more threads to generate a result for each of the two or more threads. These results are then compared using comparison hardware logic and if there is a mismatch between the results obtained, then an error or event is raised. The comparison is performed on an instruction by instruction basis so that errors are identified (and hence can be resolved) quickly.

    Decoding instructions that are modified by one or more other instructions

    公开(公告)号:US10379861B2

    公开(公告)日:2019-08-13

    申请号:US15874724

    申请日:2018-01-18

    申请人: MIPS Tech, LLC

    IPC分类号: G06F9/30 G06F9/38

    摘要: Methods and apparatus are provided for decoding instructions in a computer program wherein the instructions include one or more base instructions that are subject to modification by one or more other instructions. A decoder determines whether a first received instruction was arrived at by a non-incremental change to a program counter (i.e. a jump in the program). If the first instruction was arrived at by a non-incremental change to the program counter the decoder decodes the immediately preceding instruction to determine if the original instruction is a base instruction subject to modification by one or more other instructions. If the preceding instruction indicates that the original instruction is a base instruction an error has occurred and exception handling code is invoked.

    Logical elements with switchable connections in a reconfigurable fabric

    公开(公告)号:US10374605B2

    公开(公告)日:2019-08-06

    申请号:US16176922

    申请日:2018-10-31

    IPC分类号: H03K19/0175 H03K19/177

    摘要: Techniques are disclosed for designing a reconfigurable fabric. The reconfigurable fabric is designed using logical elements, configurable connections between and among the logical elements, and rotating circular buffers. The circular buffers contain configuration instructions. The configuration instructions control connections between and among logical elements. The logical elements change operation based on the instructions that rotate through the circular buffers. Clusters of logical elements are interconnected by a switching fabric. Each cluster contains processing elements, storage elements, and switching elements. A circular buffer within a cluster contains multiple switching instructions to control the flow of data throughout the switching fabric. The circular buffer provides a pipelined execution of switching instructions for the implementation of multiple functions. Each cluster contains multiple processing elements, and each cluster further comprises an additional circular buffer for each processing element. Logical operations are controlled by the circular buffers.

    Artificial neural network functionality within dynamic random-access memory

    公开(公告)号:US10360971B1

    公开(公告)日:2019-07-23

    申请号:US15961599

    申请日:2018-04-24

    摘要: Techniques are disclosed for artificial neural network functionality within dynamic random-access memory. A plurality of dynamic random-access cells is accessed within a memory block. Data within the plurality of dynamic random-access cells is sensed using a plurality of sense amplifiers associated with the plurality of dynamic random-access cells. A plurality of select lines coupled to the plurality of sense amplifiers is activated to facilitate the sensing of the data within the plurality of dynamic random-access cells, wherein the activating is a function of inputs to a layer within a neural network, and wherein a bit within the plurality of dynamic random-access cells is sensed by a first sense amplifier and a second sense amplifier within the plurality of sense amplifiers. Resulting data is provided based on the activating wherein the resulting data is a function of weights within the neural network.

    Video recommendation via affect
    85.
    发明授权

    公开(公告)号:US10289898B2

    公开(公告)日:2019-05-14

    申请号:US15357585

    申请日:2016-11-21

    申请人: Affectiva, Inc.

    摘要: Analysis of mental state data is provided to enable video recommendations via affect. Analysis and recommendation is made for socially shared live-stream video. Video response is evaluated based on viewing and sampling various videos. Data is captured for viewers of a video, where the data includes facial information and/or physiological data. Facial and physiological information is gathered for a group of viewers. In some embodiments, demographic information is collected and used as a criterion for visualization of affect responses to videos. In some embodiments, data captured from an individual viewer or group of viewers is used to rank videos.

    Logical elements with switchable connections for multifunction operation

    公开(公告)号:US10218357B2

    公开(公告)日:2019-02-26

    申请号:US15443612

    申请日:2017-02-27

    IPC分类号: H03K19/0175 H03K19/177

    摘要: Clusters of logical elements are interconnected by a switching fabric. Each cluster contains processing elements, storage elements, and switching elements. A circular buffer within a cluster contains multiple switching instructions to control the flow of data throughout the switching fabric. The circular buffer provides a pipelined execution of switching instructions for the implementation of multiple functions. Each cluster contains multiple processing elements, and each cluster further comprises an additional circular buffer for each processing element. Logical operations are controlled by the circular buffers.

    Audio analysis learning using video data

    公开(公告)号:US10204625B2

    公开(公告)日:2019-02-12

    申请号:US15861855

    申请日:2018-01-04

    申请人: Affectiva, Inc.

    摘要: Audio analysis learning is performed using video data. Video data is obtained, on a first computing device, wherein the video data includes images of one or more people. Audio data is obtained, on a second computing device, which corresponds to the video data. A face is identified within the video data. A first voice, from the audio data, is associated with the face within the video data. The face within the video data is analyzed for cognitive content. Audio features are extracted corresponding to the cognitive content of the video data. The audio data is segmented to correspond to an analyzed cognitive state. An audio classifier is learned, on a third computing device, based on the analyzing of the face within the video data. Further audio data is analyzed using the audio classifier.

    Translation lookaside buffer
    88.
    发明授权

    公开(公告)号:US10185665B2

    公开(公告)日:2019-01-22

    申请号:US15824613

    申请日:2017-11-28

    申请人: MIPS Tech, LLC

    摘要: Embodiments disclosed pertain to apparatuses, systems, and methods for Translation Lookaside Buffers (TLBs) that support visualization and multi-threading. Disclosed embodiments pertain to a TLB that includes a content addressable memory (CAM) with variable page size entries and a set associative memory with fixed page size entries. The CAM may include: a first set of logically contiguous entry locations, wherein the first set comprises a plurality of subsets, and each subset comprises logically contiguous entry locations for exclusive use of a corresponding virtual processing element (VPE); and a second set of logically contiguous entry locations, distinct from the first set, where the entry locations in the second set may be shared among available VPEs. The set associative memory may comprise a third set of logically contiguous entry locations shared among the available VPEs distinct from the first and second set of entry locations.