公开(公告)号：US20060205125A1

公开(公告)日：2006-09-14

申请号：US11371057

申请日：2006-03-08

申请人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Min-Seok Oh ,  Je-Hun Lee ,  Beom-Seok Cho

发明人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Min-Seok Oh ,  Je-Hun Lee ,  Beom-Seok Cho

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L29/458

摘要： A TFT substrate includes a base substrate, a gate wiring formed on the base substrate, a gate insulation layer, an activation layer, an oxidation-blocking layer, a data wiring, a protection layer and a pixel electrode. The gate wiring includes a gate line and a gate electrode. The gate insulation layer is formed on the base substrate to cover the gate wiring. The activation layer is formed on the gate insulation layer. The oxidation-blocking layer is formed on the activation layer. The data wiring includes a data line, a source electrode and a drain electrode. The source and drain electrodes are disposed on the oxidation-blocking layer therefore lowering the on-current (“Ion”) for turning on the TFT and increasing the off-current (“Ioff”) for turning off the TFT due to the oxidation-blocking layer.

摘要翻译： TFT基板包括基底基板，形成在基底基板上的栅极布线，栅极绝缘层，激活层，氧化阻挡层，数据布线，保护层和像素电极。 栅极布线包括栅极线和栅电极。 栅极绝缘层形成在基底基板上以覆盖栅极布线。 活化层形成在栅绝缘层上。 氧化阻挡层形成在活化层上。 数据线包括数据线，源电极和漏电极。 源电极和漏电极设置在氧化阻挡层上，因此降低导通电流（“I”上“），以便导通TFT并增加截止电流（”I“ “），用于关闭由于氧化阻挡层而导致的TFT。

公开(公告)号：US20060145255A1

公开(公告)日：2006-07-06

申请号：US10548562

申请日：2004-02-28

申请人： Chang-Oh Jeong ,  Beom-Seok Cho ,  Hee-Hwan Choe

发明人： Chang-Oh Jeong ,  Beom-Seok Cho ,  Hee-Hwan Choe

IPC分类号： H01L21/84

CPC分类号： H01L29/78669 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/12 ,  H01L27/124 ,  H01L29/456 ,  H01L29/4908

摘要： Disclosed are a thin film transistor substrate of an LCD device and a method of manufacturing the same. The thin film transistor substrate includes a nickel-silicide layer formed on an insulating layer pattern including silicon and a metal layer formed on the nickel-silicide layer. Nickel is coated on the insulating layer pattern including silicon and a metal material is coated on the nickel-coated layer. After that, a heat treatment is performed at about 200 to about 350° C. to obtain the nickel-silicide layer. Since the thin film transistor substrate of the LCD device is manufactured by applying the nickel-silicide wiring, a device having low resistivity and good ohmic contact property can be obtained.

公开(公告)号：US20060113670A1

公开(公告)日：2006-06-01

申请号：US11221492

申请日：2005-09-07

申请人： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Yang-Ho Bae

发明人： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Yang-Ho Bae

IPC分类号： H01L23/52

CPC分类号： H01L27/12 ,  H01L21/76838 ,  H01L23/5283 ,  H01L23/53209 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A multi-layer wiring for use with thin film transistors (TFTs), methods of manufacturing the multi-layer wiring, and TFTs employing the multi-layer wiring are provided. In one embodiment, the multi-layer wiring includes a main wiring and a sub-wiring on the main wiring. The main wiring includes a first metal and the sub-wiring includes an alloy wherein a majority of the alloy is the first metal. The multi-layer wiring can exhibit decreased electrical resistance and a reduced tendency to develop malfunctions such as hillocks or spiking. The multi-layer wiring can also exhibit improved contact characteristics with other conductive elements of TFT display devices.

摘要翻译： 提供了用于薄膜晶体管（TFT）的多层布线，多层布线的制造方法以及采用多层布线的TFT。 在一个实施例中，多层布线包括主布线和主布线上的副布线。 主配线包括第一金属，并且子布线包括其中大部分合金是第一金属的合金。 多层布线可以表现出降低的电阻和降低发展故障的倾向，如小丘或尖峰。 多层布线也可以表现出与TFT显示装置的其它导电元件的接触特性的改善。

公开(公告)号：US20060050192A1

公开(公告)日：2006-03-09

申请号：US11180989

申请日：2005-07-12

申请人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

发明人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

IPC分类号： G02F1/136

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/3276 ,  Y10S438/924

摘要： The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.

公开(公告)号：US06969889B2

公开(公告)日：2005-11-29

申请号：US10475703

申请日：2002-07-26

申请人： Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： G02F1/1343 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/336 ,  H01L21/768 ,  H01L29/786 ,  H01L51/50 ,  H05B33/12 ,  H01L27/01

CPC分类号： G02F1/136227 ,  G02F1/136213 ,  G02F2001/13629

摘要： A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire include triple layers of an adhesion layer, a Ag containing layer and a protection layer. The adhesion layer includes one of Cr, Cr alloy, Ti, Ti alloy, Mo, Mo alloy, Ta, Ta alloy, the Ag containing layer includes Ag or Ag alloy, and the protection layer includes one of IZO, Mo, Mo alloy, Cr and Cr alloy.

摘要翻译： 薄膜晶体管阵列面板包括绝缘基板，形成在绝缘基板上的栅极线。 栅极绝缘层覆盖栅极线。 在栅极绝缘层上形成半导体图形。 在栅极绝缘层和半导体图案上形成具有源电极，漏电极和数据线的数据线。 在数据线上形成保护层。 在保护层上形成通过接触孔与漏电极连接的像素电极。 栅极线和数据线包括粘合层，含Ag层和保护层的三层。 粘合层包括Cr，Cr合金，Ti，Ti合金，Mo，Mo合金，Ta，Ta合金中的一种，Ag含量为Ag或Ag合金，保护层包括IZO，Mo，Mo合金， Cr和Cr合金。