公开(公告)号：US20110024759A1

公开(公告)日：2011-02-03

申请号：US12901324

申请日：2010-10-08

申请人： Jae-Gab LEE ,  Chang-Oh Jeong ,  Myung-Mo Sung ,  Hee-Jung Yang ,  Beom-Seok Cho

发明人： Jae-Gab LEE ,  Chang-Oh Jeong ,  Myung-Mo Sung ,  Hee-Jung Yang ,  Beom-Seok Cho

IPC分类号： H01L29/786 ,  H01L21/768

CPC分类号： H01L29/78603 ,  G02F2001/136295 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458 ,  H01L29/4908 ,  H01L2224/32245

摘要： The present invention relates to a thin film transistor substrate and a metal wiring method thereof, more particularly to a thin film transistor substrate comprising self-assembled monolayers between the substrate and the metal wiring, and a metal wiring thereof. Since a thin film transistor substrate of the present invention comprises three-dimensionally cross-linked self-assembled monolayers between the Si surface and the metal wiring, it has good adhesion ability and anti-diffusion ability.

摘要翻译： 薄膜晶体管基板及其金属布线方法技术领域本发明涉及薄膜晶体管基板及其金属布线方法，更具体地涉及在基板和金属布线之间包括自组装单层的薄膜晶体管基板及其金属布线。 由于本发明的薄膜晶体管基板在Si表面和金属布线之间包含三维交联的自组装单层，因此具有良好的粘附能力和抗扩散能力。

公开(公告)号：US07304383B2

公开(公告)日：2007-12-04

申请号：US10535304

申请日：2003-10-27

申请人： Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L29/4908 ,  C22C9/00 ,  G02F1/133345 ,  G02F1/136286 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/66765

摘要： There are provided a TFT substrate for an LCD apparatus and a method of manufacturing the same. A substrate (10), a diffusion barrier layer (11) and a copper alloy layer (12) are formed on the TFT substrate, consecutively. The copper alloy includes a material from about 0.5 at % to about 15 at % to form a gate wiring layer. The material is used to form the diffusion barrier layer (11). A compound that comprises a material such as Zr, Ti, Hf, V, Ta, Ni, Cr, Nb, Co, Mn, Mo, W, Rh, Pd, Pt, etc. is deposited on the diffusion barrier layer (11) to a thickness from about 50 Å to about 5,000 Å. The deposited compound is then heat treated to convert the deposited compound into a silicide compound (11b). The transistor substrate has low resistance and high conductance. Also, etching process is simplified, and a mutual diffusion is prevented by means of the thin diffusion barrier layer.

摘要翻译： 提供了一种用于LCD装置的TFT基板及其制造方法。 连续地在TFT基板上形成基板（10），扩散阻挡层（11）和铜合金层（12）。 铜合金包括约0.5at％至约15at％的材料以形成栅极布线层。 该材料用于形成扩散阻挡层（11）。 包含诸如Zr，Ti，Hf，V，Ta，Ni，Cr，Nb，Co，Mn，Mo，W，Rh，Pd，Pt等材料的化合物沉积在扩散阻挡层（11）上， 至约50至约5000的厚度。 然后将沉积的化合物进行热处理以将沉积的化合物转化为硅化物（11b）。 晶体管衬底具有低电阻和高电导率。 此外，简化了蚀刻工艺，并且通过薄的扩散阻挡层来防止相互扩散。

公开(公告)号：US20070082434A1

公开(公告)日：2007-04-12

申请号：US11540131

申请日：2006-09-29

申请人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Beom-Seok Cho

发明人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Beom-Seok Cho

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： The present invention relates to a manufacturing method of a thin film transistor array panel. the method includes forming a gate line including a gate electrode on a substrate, forming a first insulating layer on the gate line, forming a semiconductor layer on the first insulating layer, forming an ohmic contact on the semiconductor layer, forming a data line including a source electrode and a drain electrode on the ohmic contact, depositing a second insulating layer, forming a first photoresist on the second insulating layer, etching the second insulating layer and the first insulating layer using the first photoresist as an etching mask to expose a portion of the drain electrode and a portion of the substrate, forming a pixel electrode connected to an exposed portion of the drain electrode using selective deposition, and removing the first photoresist.

摘要翻译： 本发明涉及薄膜晶体管阵列面板的制造方法。 该方法包括在基板上形成包括栅电极的栅极线，在栅极线上形成第一绝缘层，在第一绝缘层上形成半导体层，在半导体层上形成欧姆接触，形成数据线， 源电极和漏电极，沉积第二绝缘层，在第二绝缘层上形成第一光致抗蚀剂，使用第一光致抗蚀剂蚀刻第二绝缘层和第一绝缘层作为蚀刻掩模，以暴露部分 所述漏电极和所述衬底的一部分，使用选择性沉积形成连接到所述漏极的暴露部分的像素电极，以及去除所述第一光致抗蚀剂。

公开(公告)号：US20060163582A1

公开(公告)日：2006-07-27

申请号：US10539223

申请日：2003-03-26

申请人： Jae-Gab Lee ,  Chang-Oh Jeong ,  Myung-Mo Sung ,  Hee-Jung Yang ,  Beom-Seok Cho

发明人： Jae-Gab Lee ,  Chang-Oh Jeong ,  Myung-Mo Sung ,  Hee-Jung Yang ,  Beom-Seok Cho

IPC分类号： H01L29/76

CPC分类号： H01L29/78603 ,  G02F2001/136295 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458 ,  H01L29/4908 ,  H01L2224/32245

摘要： The present invention relates to a thin film transistor substrate and a metal wiring method thereof, more particularly to a thin film transistor substrate comprising self-assembled monolayers between the substrate and the metal wiring, and a metal wiring method thereof. Since a thin film transistor substrate of the present invention comprises three-dimensionally cross-linked self-assembled monolayers between the Si surface and the metal wiring, it has good adhesion ability and anti-diffusion ability.

摘要翻译： 薄膜晶体管基板及其金属布线方法技术领域本发明涉及薄膜晶体管基板及其金属布线方法，更具体地涉及在基板和金属布线之间包括自组装单层的薄膜晶体管基板及其金属布线方法。 由于本发明的薄膜晶体管基板在Si表面和金属布线之间包含三维交联的自组装单层，因此具有良好的粘附能力和抗扩散能力。

公开(公告)号：US20060151788A1

公开(公告)日：2006-07-13

申请号：US10535304

申请日：2003-10-27

申请人： Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L29/04

CPC分类号： H01L29/4908 ,  C22C9/00 ,  G02F1/133345 ,  G02F1/136286 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/66765

摘要： There are provided a TFT substrate for an LCD apparatus and a method of manufacturing the same. A substrate (10), a diffusion barrier layer (11) and a copper alloy layer (12) are formed on the TFT substrate, consecutively. The copper alloy includes a material from about 0.5 at % to about 15 at % to form a gate wiring layer. The material is used to form the diffusion barrier layer (11). A compound that comprises a material such as Zr, Ti, Hf, V, Ta, Ni, Cr, Nb, Co, Mn, Mo, W, Rh, Pd, Pt, etc. is deposited on the diffusion barrier layer (11) to a thickness from about 50 Å to about 5,000 Å. The deposited compound is then heat treated to convert the deposited compound into a silicide compound (11b). The transistor substrate has low resistance and high conductance. Also, etching process is simplified, and a mutual diffusion is prevented by means of the thin diffusion barrier layer.

摘要翻译： 提供了一种用于LCD装置的TFT基板及其制造方法。 连续地在TFT基板上形成基板（10），扩散阻挡层（11）和铜合金层（12）。 铜合金包括约0.5at％至约15at％的材料以形成栅极布线层。 该材料用于形成扩散阻挡层（11）。 包含诸如Zr，Ti，Hf，V，Ta，Ni，Cr，Nb，Co，Mn，Mo，W，Rh，Pd，Pt等材料的化合物沉积在扩散阻挡层（11）上， 至约50至约5000的厚度。 然后将沉积的化合物进行热处理以将沉积的化合物转化为硅化物（11b）。 晶体管衬底具有低电阻和高电导率。 此外，简化了蚀刻工艺，并且通过薄的扩散阻挡层来防止相互扩散。

公开(公告)号：US20050242401A1

公开(公告)日：2005-11-03

申请号：US11170251

申请日：2005-06-29

申请人： Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： G02F1/1343 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/336 ,  H01L21/768 ,  H01L29/786 ,  H01L51/50 ,  H05B33/12 ,  H01L29/76

CPC分类号： G02F1/136227 ,  G02F1/136213 ,  G02F2001/13629

摘要： A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire include triple layers of an adhesion layer, a Ag containing layer and a protection layer. The adhesion layer includes one of Cr, Cr alloy, Ti, Ti alloy, Mo, Mo alloy, Ta and Ta alloy, the Ag containing layer includes Ag or Ag alloy, and the protection layer includes one of IZO, Mo, Mo alloy, Cr and Cr alloy.

摘要翻译： 薄膜晶体管阵列面板包括绝缘基板，形成在绝缘基板上的栅极线。 栅极绝缘层覆盖栅极线。 在栅极绝缘层上形成半导体图形。 在栅极绝缘层和半导体图案上形成具有源电极，漏电极和数据线的数据线。 在数据线上形成保护层。 在保护层上形成通过接触孔与漏电极连接的像素电极。 栅极线和数据线包括粘合层，含Ag层和保护层的三层。 粘合层包括Cr，Cr合金，Ti，Ti合金，Mo，Mo合金，Ta和Ta合金中的一种，含Ag层包括Ag或Ag合金，保护层包括IZO，Mo，Mo合金， Cr和Cr合金。

公开(公告)号：US06716660B2

公开(公告)日：2004-04-06

申请号：US10247727

申请日：2002-09-20

申请人： Chang-Oh Jeong ,  Jae-Gab Lee ,  Beom-Seok Cho

发明人： Chang-Oh Jeong ,  Jae-Gab Lee ,  Beom-Seok Cho

IPC分类号： H01L2100

CPC分类号： H01L27/124 ,  G02F1/136286 ,  H01L23/53242 ,  H01L23/53247 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one aspect of the present invention, the thin film transistor array substrate basically includes a gate line assembly based on an Ag alloy. The Ag alloy comprises Ag and at least one of alloy elements and the alloy elements each bearing a low melting point. The gate line assembly comprises a gate electrode and a gate line. A data line assembly crosses over the gate line assembly while being insulated from the gate line assembly. The data line assembly comprises a source electrode, a drain electrode and a data line. A semiconductor layer contacts the source electrode and the drain electrode. The semiconductor layer forms a thin film transistor together with the gate electrode, the source electrode and the drain electrode. A pixel electrode is connected to the drain electrode.

摘要翻译： 根据本发明的一个方面，薄膜晶体管阵列基板基本上包括基于Ag合金的栅极线组件。 Ag合金包含Ag和至少一种合金元素和各自具有低熔点的合金元素。 栅极线组件包括栅电极和栅极线。 数据线组件在与栅极线组件绝缘的同时跨过栅极线组件。 数据线组件包括源电极，漏电极和数据线。 半导体层接触源电极和漏电极。 半导体层与栅电极，源电极和漏电极一起形成薄膜晶体管。 像素电极连接到漏电极。

公开(公告)号：US08372701B2

公开(公告)日：2013-02-12

申请号：US12576217

申请日：2009-10-08

申请人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L21/00

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/124

摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

公开(公告)号：US08252639B2

公开(公告)日：2012-08-28

申请号：US12951981

申请日：2010-11-22

申请人： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

发明人： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

IPC分类号： H01L21/00

CPC分类号： H01L27/124 ,  H01L27/1288 ,  H01L29/12 ,  H01L29/458

摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

摘要翻译： 本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在所述栅极绝缘层上且与所述栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地接触扩散阻挡层并面对栅电极上的源电极; 以及电连接到漏电极的像素电极。

公开(公告)号：US07998786B2

公开(公告)日：2011-08-16

申请号：US12369839

申请日：2009-02-12

申请人： Je-Hun Lee ,  Jae-Kyeong Lee ,  Chang-Oh Jeong ,  Beom-Seok Cho

发明人： Je-Hun Lee ,  Jae-Kyeong Lee ,  Chang-Oh Jeong ,  Beom-Seok Cho

IPC分类号： H01L21/00

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L29/458 ,  H01L29/4908

摘要： Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111).

摘要翻译： 在含有至少一个氧，氮和碳的前体气体的存在下，在基板上沉积钼以形成钼层，形成用于较大平板显示器的多层布线。 铝层沉积在钼层上。 可以在铝层上形成另一金属层。 钼层具有面心立方（FCC）晶格结构，其优选取向为（111）。