公开(公告)号：US07741641B2

公开(公告)日：2010-06-22

申请号：US11371057

申请日：2006-03-08

申请人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Min-Seok Oh ,  Je-Hun Lee ,  Beom-Seok Cho

发明人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Min-Seok Oh ,  Je-Hun Lee ,  Beom-Seok Cho

IPC分类号： H01L29/43 ,  H01L29/786

CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L29/458

摘要： A TFT substrate includes a base substrate, a gate wiring formed on the base substrate, a gate insulation layer, an activation layer, an oxidation-blocking layer, a data wiring, a protection layer and a pixel electrode. The gate wiring includes a gate line and a gate electrode. The gate insulation layer is formed on the base substrate to cover the gate wiring. The activation layer is formed on the gate insulation layer. The oxidation-blocking layer is formed on the activation layer. The data wiring includes a data line, a source electrode and a drain electrode. The source and drain electrodes are disposed on the oxidation-blocking layer therefore lowering the on-current (“Ion”) for turning on the TFT and increasing the off-current (“Ioff”) for turning off the TFT due to the oxidation-blocking layer.

摘要翻译： TFT基板包括基底基板，形成在基底基板上的栅极布线，栅极绝缘层，激活层，氧化阻挡层，数据布线，保护层和像素电极。 栅极布线包括栅极线和栅电极。 栅极绝缘层形成在基底基板上以覆盖栅极布线。 活化层形成在栅绝缘层上。 氧化阻挡层形成在活化层上。 数据线包括数据线，源电极和漏电极。 源电极和漏电极设置在氧化阻挡层上，因此降低用于导通TFT的导通电流（“Ion”），并且由于氧化阻挡层而增加关闭TFT的截止电流（“Ioff”）， 阻挡层。

公开(公告)号：US20060205125A1

公开(公告)日：2006-09-14

申请号：US11371057

申请日：2006-03-08

申请人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Min-Seok Oh ,  Je-Hun Lee ,  Beom-Seok Cho

发明人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Min-Seok Oh ,  Je-Hun Lee ,  Beom-Seok Cho

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L29/458

摘要： A TFT substrate includes a base substrate, a gate wiring formed on the base substrate, a gate insulation layer, an activation layer, an oxidation-blocking layer, a data wiring, a protection layer and a pixel electrode. The gate wiring includes a gate line and a gate electrode. The gate insulation layer is formed on the base substrate to cover the gate wiring. The activation layer is formed on the gate insulation layer. The oxidation-blocking layer is formed on the activation layer. The data wiring includes a data line, a source electrode and a drain electrode. The source and drain electrodes are disposed on the oxidation-blocking layer therefore lowering the on-current (“Ion”) for turning on the TFT and increasing the off-current (“Ioff”) for turning off the TFT due to the oxidation-blocking layer.

摘要翻译： TFT基板包括基底基板，形成在基底基板上的栅极布线，栅极绝缘层，激活层，氧化阻挡层，数据布线，保护层和像素电极。 栅极布线包括栅极线和栅电极。 栅极绝缘层形成在基底基板上以覆盖栅极布线。 活化层形成在栅绝缘层上。 氧化阻挡层形成在活化层上。 数据线包括数据线，源电极和漏电极。 源电极和漏电极设置在氧化阻挡层上，因此降低导通电流（“I”上“），以便导通TFT并增加截止电流（”I“ “），用于关闭由于氧化阻挡层而导致的TFT。

公开(公告)号：US07172913B2

公开(公告)日：2007-02-06

申请号：US11082967

申请日：2005-03-18

申请人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

发明人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  G02F2001/136236 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733

摘要： A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

公开(公告)号：US20070102770A1

公开(公告)日：2007-05-10

申请号：US11619451

申请日：2007-01-03

申请人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

发明人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

IPC分类号： H01L29/76

CPC分类号： H01L27/1288 ,  G02F2001/136236 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733

摘要： A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

公开(公告)号：US20050221546A1

公开(公告)日：2005-10-06

申请号：US11082967

申请日：2005-03-18

申请人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

发明人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

IPC分类号： G02F1/1368 ,  G09F9/30 ,  G09G3/36 ,  G09G3/38 ,  H01L21/00 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L27/1288 ,  G02F2001/136236 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733

摘要： A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

公开(公告)号：US08372701B2

公开(公告)日：2013-02-12

申请号：US12576217

申请日：2009-10-08

申请人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L21/00

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/124

摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

公开(公告)号：US07352004B2

公开(公告)日：2008-04-01

申请号：US11249500

申请日：2005-10-14

申请人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L31/00

CPC分类号： H01L27/3279 ,  H01L27/124 ,  H01L27/1288 ,  H01L51/0023 ,  H01L51/56

摘要： The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.

摘要翻译： 本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

公开(公告)号：US20060102907A1

公开(公告)日：2006-05-18

申请号：US11228852

申请日：2005-09-16

申请人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L29/04

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/124

摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

摘要翻译： 本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

公开(公告)号：US07619254B2

公开(公告)日：2009-11-17

申请号：US11228852

申请日：2005-09-16

申请人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/124

摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

摘要翻译： 本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

公开(公告)号：US07550768B2

公开(公告)日：2009-06-23

申请号：US11944130

申请日：2007-11-21

申请人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

发明人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/76 ,  H01L31/112 ,  H01L29/15

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/3276 ,  Y10S438/924

摘要： The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.

摘要翻译： 本发明提供一种TFT阵列面板及其制造方法，其特征在于，具有含有Al的金属的下层和包含钼（Mo）的钼合金（Mo合金）的上层的信号线，至少包括 铌（Nb），钒（V）和钛（Ti）之一。 因此，防止在蚀刻工艺中可能出现的底切，突出和小鼠咬合，并且提供具有低电阻率和良好接触特性的信号线的TFT阵列面板。