公开(公告)号：US20080013371A1

公开(公告)日：2008-01-17

申请号：US11769383

申请日：2007-06-27

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C16/02

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C29/88 ,  G11C2211/5621 ,  G11C2211/5646

Abstract: A memory cell array includes a plurality of memory cells enabled to store multi-value data. A bit-line control circuit includes data storage circuits connected to bit-lines and each store one of a plurality of sets of page data included in the multi-value data, the bit-line control circuit controlling bit-line voltages applied to the bit-lines. A word-line control circuit controls a word-line voltage applied to a word-line. A control circuit controls the word-line control circuit and the bit-line control circuit. The control circuit performs a mode in which, to distinguish a fault block, all or specific memory cells in a fault block may be written so that all or specific memory cells in the fault block have a threshold voltage higher than a word-line voltage applied to a selected word-line when reading a first page data of the sets of page data.

Abstract translation: 存储单元阵列包括能够存储多值数据的多个存储单元。 位线控制电路包括连接到位线的数据存储电路，并且每个存储包括在多值数据中的多组页数据中的一个，位线控制电路控制施加到位的位线电压 线。 字线控制电路控制施加到字线的字线电压。 控制电路控制字线控制电路和位线控制电路。 控制电路执行这样的模式，为了区分故障块，可以写入故障块中的全部或特定存储单元，使得故障块中的全部或特定存储单元的阈值电压高于施加的字线电压 当读取页面数据集合的第一页数据时，到所选择的字线。

公开(公告)号：US20060227624A1

公开(公告)日：2006-10-12

申请号：US11167301

申请日：2005-06-28

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C7/10

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2207/2245 ,  G11C2211/5646

Abstract: A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged to store multi-value data; a sense amplifier circuit configured to read data of and write data in the memory cell array; and a controller configured to control data read and write of the memory cell array, wherein the controller has such a function as, when an upper page data write sequence ends in failure, the upper page data being one to be written into an area of the memory cell array where lower page data has already been written, to cache the lower page data read out of the memory cell array and held in the sense amplifier circuit.

Abstract translation: 半导体存储器件包括：存储单元阵列，其中电可重写和非易失性存储器单元被布置为存储多值数据; 读出放大器电路，被配置为读取存储单元阵列中的数据并写入数据; 以及控制器，其被配置为控制所述存储单元阵列的数据读取和写入，其中所述控制器具有如下功能：当上页数据写入序列以故障结束时，所述上页数据为要写入所述存储单元阵列的区域中的一个 存储单元阵列，其中已经写入较低页数据，以缓存从存储单元阵列读出并保持在读出放大器电路中的下部页数据。

公开(公告)号：US06434080B1

公开(公告)日：2002-08-13

申请号：US09707845

申请日：2000-11-08

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C800

CPC classification number: G11C16/3445 ,  G11C5/145 ,  G11C8/08 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3459

Abstract: A semiconductor memory has a memory cell array, a boosted voltage generator to generate a boosted voltage and a decoder to select memory cells in said memory cell array in response to an address signal. The voltage generator is activated in response to input of a first command, and kept active for a period of repeated input of a second command to control for the voltage generator, following the first command. The semiconductor memory may be provided with a regular operation mode in which the voltage generator is controlled to be in an active or inactive state by means of a first command signal in response to a predetermined signal, and a successive operation mode in which the voltage generator is kept active by a second command signal in response to another predetermined signal.

Abstract translation: 半导体存储器具有存储单元阵列，用于产生升压电压的升压电压发生器和解码器，以响应于地址信号选择所述存储单元阵列中的存储单元。 电压发生器响应于第一命令的输入被激活，并且在第一命令之后保持有效的第二命令的重复输入的周期以控制电压发生器。 半导体存储器可以被提供有常规操作模式，其中电压发生器通过响应于预定信号的第一命令信号被控制为处于活动或非活动状态，以及连续操作模式，其中电压发生器 响应于另一个预定信号由第二命令信号保持活动。

公开(公告)号：US06240019B1

公开(公告)日：2001-05-29

申请号：US09471489

申请日：1999-12-23

Applicant: Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

Inventor： Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

IPC: G11C1606

CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C2216/20

Abstract: A non-volatile semiconductor memory device according to the invention comprises a memory cell array having a plurality of non-volatile memory cells, and a write state machine controlling a voltage applied to a memory cell selected from the memory cell array and a voltage application period, in accordance with each of reading of data from the selected memory cell, writing of data into the selected memory cell, and erasion of data from the selected memory. The write state machine executes writing, under a first writing condition, on a predetermined number of memory cells included in the memory cell array, and executes writing on memory cells other than the predetermined number of memory cells, under a second writing condition set in accordance with a result of the writing executed under the first writing condition.

Abstract translation: 根据本发明的非易失性半导体存储器件包括具有多个非易失性存储单元的存储单元阵列，以及控制施加到从存储单元阵列选择的存储单元的电压的写状态机和施加电压的周期 根据从所选择的存储器单元读取数据的每一个，将数据写入所选存储单元，以及从所选存储器中擦除数据。 写入状态机在第一写入条件下执行包含在存储单元阵列中的预定数量的存储单元上的写入，并且在按照相应设置的第二写入条件下执行对除了预定数量的存储单元之外的存储单元的写入 其结果是在第一写入条件下执行写入。