公开(公告)号：US09043679B2

公开(公告)日：2015-05-26

申请号：US13719479

申请日：2012-12-19

Applicant: Hitoshi Shiga ,  Hidetaka Tsuji

Inventor： Hitoshi Shiga ,  Hidetaka Tsuji

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/04

CPC classification number: G06F11/1008 ,  G06F11/1072 ,  G11C2029/0411

Abstract: A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation. The external controller includes an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data. The internal controller outputs the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.

Abstract translation: 存储器件包括存储数据的存储器芯片和控制存储器芯片的外部控制器。 存储器芯片包括被配置为存储两个或多个位的数据的多个存储器单元; 以及内部控制器，其执行包括下页和上页程序操作的页面数据的编程操作，并且对包括下页和上页读操作的页数据执行读操作。 外部控制器包括纠错单元，对要编程到存储单元阵列中的数据进行纠错编码，并对数据执行纠错解码。 在上层读取操作中，内部控制器将读取页数据从存储单元阵列输出到外部控制器，而不管高层编程操作是否完成。

公开(公告)号：US07978512B2

公开(公告)日：2011-07-12

申请号：US12557898

申请日：2009-09-11

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00 ,  G11C2211/5641 ,  H01L27/11521

Abstract: A semiconductor memory system includes: a memory cell array having a plurality of memory cells arranged therein, the plurality of memory cells capable of storing N bits of information in each memory cell (where N is a natural number more than 3, other than a power of two); a control circuit configured to control read, write, and erase operations on the memory cell array; and an ECC circuit configured to correct data read from the memory cell array, based on redundant data. The memory cells that share one of word lines and can be written or read at a time are configured to store multiple pages of data therein. A total amount of data stored in the multiple pages is set to a power-of-two number of bits, and the redundant data is stored in a residual portion of the multiple pages.

Abstract translation: 半导体存储器系统包括：存储单元阵列，其中布置有多个存储器单元，所述多个存储单元能够在每个存储单元中存储N位信息（其中N是大于3的自然数，除了功率 的两个）; 控制电路，被配置为控制对所述存储单元阵列的读，写和擦除操作; 以及ECC电路，被配置为基于冗余数据校正从存储单元阵列读取的数据。 共享字线之一并且可以一次写入或读取的存储单元被配置为在其中存储多页数据。 存储在多页中的数据的总量被设置为两位数，并且冗余数据被存储在多页的剩余部分中。

公开(公告)号：US07843724B2

公开(公告)日：2010-11-30

申请号：US11863915

申请日：2007-09-28

Applicant: Hitoshi Shiga ,  Susumu Fujimura ,  Yoshihiko Shindo

Inventor： Hitoshi Shiga ,  Susumu Fujimura ,  Yoshihiko Shindo

IPC: G11C7/00

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5646

Abstract: A nonvolatile semiconductor memory that includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section. The data reading and programming cortrol section includes: an adjacent memory cell data reading section; an adjacent memory cell data memory section; a reading voltage level control section; a data reading section for reading the data from a first memory cell at a plurality of reading voltages corresponding to a plurality of predetermined reading voltage verify levels controlled using the reading voltage level control section; and a data determining section for deterraining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section.

Abstract translation: 一种非易失性半导体存储器，包括：包括多个电可写入存储单元的存储单元阵列; 连接到所述多个存储单元的多个字线和多个位线; 和数据读取和编程控制部分。 数据读取和编程cortrol部分包括：相邻的存储单元数据读取部分; 相邻存储单元数据存储器部分; 读取电压电平控制部; 数据读取部分，用于以对应于使用读取电压电平控制部分控制的多个预定读取电压验证电平的多个读取电压读取来自第一存储器单元的数据; 以及数据确定部分，用于基于由数据读取部分读取的数据来确定在第一存储器单元中编程4值数据的哪个数据。

公开(公告)号：US07522452B2

公开(公告)日：2009-04-21

申请号：US11769383

申请日：2007-06-27

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C29/88 ,  G11C2211/5621 ,  G11C2211/5646

Abstract: A memory cell array includes a plurality of memory cells enabled to store multi-value data. A bit-line control circuit includes data storage circuits connected to bit-lines and each store one of a plurality of sets of page data included in the multi-value data, the bit-line control circuit controlling bit-line voltages applied to the bit-lines. A word-line control circuit controls a word-line voltage applied to a word-line. A control circuit controls the word-line control circuit and the bit-line control circuit. The control circuit performs a mode in which, to distinguish a fault block, all or specific memory cells in a fault block may be written so that all or specific memory cells in the fault block have a threshold voltage higher than a word-line voltage applied to a selected word-line when reading a first page data of the sets of page data.

Abstract translation: 存储单元阵列包括能够存储多值数据的多个存储单元。 位线控制电路包括连接到位线的数据存储电路，并且每个存储包括在多值数据中的多组页数据中的一个，位线控制电路控制施加到位的位线电压 线。 字线控制电路控制施加到字线的字线电压。 控制电路控制字线控制电路和位线控制电路。 控制电路执行这样的模式，为了区分故障块，可以写入故障块中的全部或特定存储单元，使得故障块中的全部或特定存储单元的阈值电压高于施加的字线电压 当读取页面数据集合的第一页数据时，到所选择的字线。

公开(公告)号：US20060227624A1

公开(公告)日：2006-10-12

申请号：US11167301

申请日：2005-06-28

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C7/10

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2207/2245 ,  G11C2211/5646

Abstract: A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged to store multi-value data; a sense amplifier circuit configured to read data of and write data in the memory cell array; and a controller configured to control data read and write of the memory cell array, wherein the controller has such a function as, when an upper page data write sequence ends in failure, the upper page data being one to be written into an area of the memory cell array where lower page data has already been written, to cache the lower page data read out of the memory cell array and held in the sense amplifier circuit.

Abstract translation: 半导体存储器件包括：存储单元阵列，其中电可重写和非易失性存储器单元被布置为存储多值数据; 读出放大器电路，被配置为读取存储单元阵列中的数据并写入数据; 以及控制器，其被配置为控制所述存储单元阵列的数据读取和写入，其中所述控制器具有如下功能：当上页数据写入序列以故障结束时，所述上页数据为要写入所述存储单元阵列的区域中的一个 存储单元阵列，其中已经写入较低页数据，以缓存从存储单元阵列读出并保持在读出放大器电路中的下部页数据。

公开(公告)号：US06434080B1

公开(公告)日：2002-08-13

申请号：US09707845

申请日：2000-11-08

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C800

CPC classification number: G11C16/3445 ,  G11C5/145 ,  G11C8/08 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3459

Abstract: A semiconductor memory has a memory cell array, a boosted voltage generator to generate a boosted voltage and a decoder to select memory cells in said memory cell array in response to an address signal. The voltage generator is activated in response to input of a first command, and kept active for a period of repeated input of a second command to control for the voltage generator, following the first command. The semiconductor memory may be provided with a regular operation mode in which the voltage generator is controlled to be in an active or inactive state by means of a first command signal in response to a predetermined signal, and a successive operation mode in which the voltage generator is kept active by a second command signal in response to another predetermined signal.

Abstract translation: 半导体存储器具有存储单元阵列，用于产生升压电压的升压电压发生器和解码器，以响应于地址信号选择所述存储单元阵列中的存储单元。 电压发生器响应于第一命令的输入被激活，并且在第一命令之后保持有效的第二命令的重复输入的周期以控制电压发生器。 半导体存储器可以被提供有常规操作模式，其中电压发生器通过响应于预定信号的第一命令信号被控制为处于活动或非活动状态，以及连续操作模式，其中电压发生器 响应于另一个预定信号由第二命令信号保持活动。

公开(公告)号：US06240019B1

公开(公告)日：2001-05-29

申请号：US09471489

申请日：1999-12-23

Applicant: Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

Inventor： Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

IPC: G11C1606

CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C2216/20

Abstract: A non-volatile semiconductor memory device according to the invention comprises a memory cell array having a plurality of non-volatile memory cells, and a write state machine controlling a voltage applied to a memory cell selected from the memory cell array and a voltage application period, in accordance with each of reading of data from the selected memory cell, writing of data into the selected memory cell, and erasion of data from the selected memory. The write state machine executes writing, under a first writing condition, on a predetermined number of memory cells included in the memory cell array, and executes writing on memory cells other than the predetermined number of memory cells, under a second writing condition set in accordance with a result of the writing executed under the first writing condition.

Abstract translation: 根据本发明的非易失性半导体存储器件包括具有多个非易失性存储单元的存储单元阵列，以及控制施加到从存储单元阵列选择的存储单元的电压的写状态机和施加电压的周期 根据从所选择的存储器单元读取数据的每一个，将数据写入所选存储单元，以及从所选存储器中擦除数据。 写入状态机在第一写入条件下执行包含在存储单元阵列中的预定数量的存储单元上的写入，并且在按照相应设置的第二写入条件下执行对除了预定数量的存储单元之外的存储单元的写入 其结果是在第一写入条件下执行写入。

公开(公告)号：US08902662B2

公开(公告)日：2014-12-02

申请号：US13226180

申请日：2011-09-06

Applicant: Hitoshi Shiga ,  Masahiro Yoshihara

Inventor： Hitoshi Shiga ,  Masahiro Yoshihara

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/30 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: According to one embodiment, a memory system includes a first nonvolatile semiconductor memory, a second nonvolatile semiconductor memory and a controller. The first memory has memory cells and executes a first operation that is at least one of write, read, and erase operations with respect to the memory cells. The first operation includes a first sub-operation and a second-sub operation that consume a current which is equal to or higher than a predetermined current. The second memory has memory cells and executes a second operation that is at least one of write, read, and erase operations with respect to the memory cells. The second operation includes a third sub-operation and a fourth sub-operation that consume a current which is equal to or higher than the predetermined current. The controller controls the first operation and the second operation of the first memory and the second memory.

Abstract translation: 根据一个实施例，存储器系统包括第一非易失性半导体存储器，第二非易失性半导体存储器和控制器。 第一存储器具有存储器单元并且执行与存储器单元相关的写入，读取和擦除操作中的至少一个的第一操作。 第一操作包括消耗等于或高于预定电流的电流的第一子操作和第二子操作。 第二存储器具有存储单元并且执行与存储单元相关的写入，读取和擦除操作中的至少一个的第二操作。 第二操作包括消耗等于或高于预定电流的电流的第三子操作和第四子操作。 控制器控制第一存储器和第二存储器的第一操作和第二操作。

公开(公告)号：US08432737B2

公开(公告)日：2013-04-30

申请号：US13217512

申请日：2011-08-25

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C11/34

CPC classification number: G11C29/025 ,  G11C16/26 ,  G11C2029/1202 ,  G11C2029/5006

Abstract: When performing a word line leak test to determine a leak state of the word lines, the control circuit applies, from the voltage control circuit to the word lines connected to the memory cell array written with test pattern data, voltages corresponding to the test pattern data. Thereafter, it switches the transfer transistors to a nonconductive state, thereby setting the word lines in a floating state. After a lapse of a certain time from switching of the transfer transistors to a nonconductive state, it activates the sense amplifier circuit to perform a read operation in the memory cell array. Then it compares a result of the read operation with an expectation value corresponding to the test pattern data.

Abstract translation: 当进行字线泄漏测试以确定字线的泄漏状态时，控制电路从电压控制电路向连接到用测试图形数据写入的存储单元阵列的字线施加与测试图案数据相对应的电压 。 此后，它将传输晶体管切换到非导通状态，从而将字线设置为浮置状态。 在从转换晶体管切换到非导通状态经过一段时间之后，它激活读出放大器电路，以在存储单元阵列中执行读取操作。 然后将读取操作的结果与对应于测试图案数据的期望值进行比较。

公开(公告)号：US08036034B2

公开(公告)日：2011-10-11

申请号：US12564425

申请日：2009-09-22

Applicant: Hitoshi Shiga ,  Yoshihisa Kondo

Inventor： Hitoshi Shiga ,  Yoshihisa Kondo

IPC: G11C16/26

CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C29/00

Abstract: A semiconductor storage device comprises: a sense amplifier circuit; a first data retaining circuit and a second data retaining circuit configured to retain data and threshold voltage information, the second data retaining circuit output the data and the threshold voltage information to the outside; and a control circuit configured to control operation. The sense amplifier circuit is configured to perform a data-read operation and a threshold-voltage-information read operation at the same time. The control circuit is configured to control read operations so that either one of the data or the threshold voltage information for which a read operation is finished earlier is output from the second data retaining circuit, and the other one of the data or the threshold voltage information for which a read operation is not finished yet is read from a memory cell array and retained in the first data retaining circuit.

Abstract translation: 半导体存储装置包括：读出放大器电路; 第一数据保持电路和第二数据保持电路，被配置为保持数据和阈值电压信息，第二数据保持电路将数据和阈值电压信息输出到外部; 以及控制电路，被配置为控制操作。 感测放大器电路被配置为同时执行数据读取操作和阈值电压信息读取操作。 控制电路被配置为控制读取操作，使得先前完成读取操作的数据或阈值电压信息中的任何一个从第二数据保持电路输出，另一个数据或阈值电压信息 读取操作尚未完成，从存储单元阵列中读出并保留在第一数据保持电路中。