公开(公告)号：US20120306459A1

公开(公告)日：2012-12-06

申请号：US13478015

申请日：2012-05-22

申请人： Jyun-Che Ho ,  Chien-Fu Tang ,  Isaac Y. Chen ,  Shao-Hung Lu ,  Tzu-Chen Lin

发明人： Jyun-Che Ho ,  Chien-Fu Tang ,  Isaac Y. Chen ,  Shao-Hung Lu ,  Tzu-Chen Lin

IPC分类号： G05F1/70

CPC分类号： H05B33/0818

摘要： The present invention discloses a power factor correction circuit, a control circuit therefor and a method for driving a power factor correction circuit. The power factor correction circuit receives rectified power obtained by rectifying AC power, and corrects the power factor thereof. The power factor correction circuit includes an inductor, and it generates a reference signal as a limit for the inductor current. The reference signal is proportional to Comp/Vin, wherein Comp is a signal relating to a feedback signal, and Vin is a voltage signal relating to the AC power or the rectified power.

摘要翻译： 本发明公开了一种功率因数校正电路及其控制电路及驱动功率因数校正电路的方法。 功率因数校正电路接收通过整流交流电源而得到的整流功率，校正其功率因数。 功率因数校正电路包括电感器，并产生参考信号作为电感电流的限制。 参考信号与Comp / Vin成比例，其中Comp是与反馈信号相关的信号，Vin是与AC电力或整流功率有关的电压信号。

公开(公告)号：US20120056683A1

公开(公告)日：2012-03-08

申请号：US13221011

申请日：2011-08-30

申请人： CHIEN-FU TANG ,  ISAAC Y. CHEN

发明人： CHIEN-FU TANG ,  ISAAC Y. CHEN

IPC分类号： H03B29/00

CPC分类号： H03K3/84 ,  G06F1/04 ,  H02M1/44 ,  H03B29/00 ,  H03K17/16

摘要： An oscillator generates a clock signal according to a voltage, a current and a capacitance, and a frequency jitter circuit and method use a random number to modulate the voltage, the current or the capacitance, or a count value to modulate the capacitance, to jitter the frequency of the clock signal.

摘要翻译： 振荡器根据电压，电流和电容产生时钟信号，并且频率抖动电路和方法使用随机数来调制电压，电流或电容或计数值以调制电容到抖动 时钟信号的频率。

公开(公告)号：US20120008345A1

公开(公告)日：2012-01-12

申请号：US13173417

申请日：2011-06-30

申请人： CHIEN-FU TANG ,  ISAAC Y. CHEN ,  LIANG-PIN TAI

发明人： CHIEN-FU TANG ,  ISAAC Y. CHEN ,  LIANG-PIN TAI

IPC分类号： H02M3/335

CPC分类号： H02M3/33515

摘要： An apparatus and method for output voltage calibration of a primary feedback flyback power module extract the difference between the output voltage of the power module and a target value, and according thereto, calibrate a reference voltage which is used in regulation of the output voltage, to thereby calibrate the output voltage to be the target value.

摘要翻译： 用于主反馈反激功率模块的输出电压校准的装置和方法提取功率模块的输出电压与目标值之间的差异，并且根据该装置和方法校准用于调节输出电压的参考电压， 从而将输出电压校准为目标值。

公开(公告)号：US20120002732A1

公开(公告)日：2012-01-05

申请号：US13175906

申请日：2011-07-04

申请人： Isaac Y. Chen

发明人： Isaac Y. Chen

IPC分类号： H04L25/34

CPC分类号： H04L25/4923 ,  H04L5/04 ,  H04L7/044

摘要： The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.

摘要翻译： 本发明公开了一种单线异步串行接口，以及一种通过一条传输线传输命令和数据的方法，其中传输线能传输三电平状态信号。 所公开的接口包括：信号电平提取电路，接收通过线路传输的信号，并根据接收到的信号输出逻辑或功能位; 根据功能位产生时钟信号的时钟提取电路和由时钟信号控制并存储逻辑比特的存储器电路。 所公开的方法包括：使用两个电平状态来表示逻辑0和逻辑1，并且将第三个状态用作功能位; 以及通过所述组内的功能位的存在来确定一组信号是否是命令或数据。

公开(公告)号：US08064534B2

公开(公告)日：2011-11-22

申请号：US12684440

申请日：2010-01-08

申请人： Isaac Y. Chen

发明人： Isaac Y. Chen

IPC分类号： H04L25/49

CPC分类号： H04L25/4923 ,  H04L5/04 ,  H04L7/044

摘要： The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.

摘要翻译： 本发明公开了一种单线异步串行接口，以及一种通过一条传输线传输命令和数据的方法，其中传输线能传输三电平状态信号。 所公开的接口包括：信号电平提取电路，接收通过线路传输的信号，并根据接收到的信号输出逻辑或功能位; 根据功能位产生时钟信号的时钟提取电路和由时钟信号控制并存储逻辑比特的存储器电路。 所公开的方法包括：使用两个电平状态来表示逻辑0和逻辑1，并且将第三个状态用作功能位; 以及通过所述组内的功能位的存在来确定一组信号是否是命令或数据。

公开(公告)号：US20110260799A1

公开(公告)日：2011-10-27

申请号：US13087515

申请日：2011-04-15

申请人： SHAO-HUNG LU ,  ISAAC Y. CHEN

发明人： SHAO-HUNG LU ,  ISAAC Y. CHEN

IPC分类号： H03L7/00

CPC分类号： H03L7/099

摘要： A frequency setting circuit and method for an integrated circuit detect the voltage at a pin of the integrated circuit during a frequency setting period, and determine a frequency setting signal according to the detected voltage to set the frequency of a clock provided by an oscillator in the integrated circuit. After setting the frequency, the frequency setting circuit and method store the frequency setting signal and stop detecting the voltage at the pin. Thus the pin can be used for other functions.

摘要翻译： 用于集成电路的频率设定电路和方法在频率设定期间检测集成电路的引脚上的电压，并根据检测到的电压来确定频率设定信号，以将振荡器提供的时钟的频率设置在 集成电路。 设定频率后，频率设定电路和方法存储频率设定信号，停止检测引脚电压。 因此，该引脚可用于其他功能。

公开(公告)号：US20110233716A1

公开(公告)日：2011-09-29

申请号：US13048057

申请日：2011-03-15

申请人： CHIEN-FU TANG ,  ISAAC Y. CHEN

发明人： CHIEN-FU TANG ,  ISAAC Y. CHEN

IPC分类号： H01L29/06

CPC分类号： G11C16/30 ,  H01L23/3192 ,  H01L23/525 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit structure of an ultra high voltage level shifter includes a low voltage substrate having the electronic elements of the ultra high voltage level shifter thereon, an ultra high voltage redistribution layer, and a passivation layer between the substrate and the redistribution layer to prevent dielectric breakdown between the redistribution layer and the substrate.

摘要翻译： 超高电压电平移位器的电路结构包括其上具有超高电平电平移位器的电子元件的低电压基板，超高电压再分布层以及衬底和再分配层之间的钝化层，以防止电介质击穿 在再分布层和衬底之间。

公开(公告)号：US20110187430A1

公开(公告)日：2011-08-04

申请号：US12700146

申请日：2010-02-04

申请人： Chien Fu Tang ,  Isaac Y. Chen

发明人： Chien Fu Tang ,  Isaac Y. Chen

IPC分类号： H03K3/289

CPC分类号： H03K3/289

摘要： The present invention discloses a multi-chip module with master-slave analog signal transmission function. The multi-chip module comprises: a master chip having a first setting input pin for receiving an analog setting signal to generate an analog setting in the master chip, and the master chip duplicating the analog setting to output a first analog output; and a first slave chip for receiving the first analog output from the master chip to generate an internal setting of the first slave chip.

摘要翻译： 本发明公开了一种具有主从模拟信号传输功能的多芯片模块。 多芯片模块包括：主芯片，具有第一设置输入引脚，用于接收模拟设置信号以在主芯片中产生模拟设置，主芯片复制模拟设置以输出第一模拟输出; 以及第一从芯片，用于从主芯片接收第一模拟输出以产生第一从芯片的内部设置。

公开(公告)号：US20110169546A1

公开(公告)日：2011-07-14

申请号：US12985587

申请日：2011-01-06

申请人： YUEH-MING CHEN ,  ISAAC Y. CHEN ,  SHAO-HUNG LU

发明人： YUEH-MING CHEN ,  ISAAC Y. CHEN ,  SHAO-HUNG LU

IPC分类号： G06G7/16

CPC分类号： G06G7/16

摘要： A mix mode wide range multiplier and method are provided for multiplying a first signal by a second signal to generate an output signal. A reference signal is generated according to a first gain and a reference value, the output signal is generated according to a second gain and the first signal, a target value is generated according to the second signal, the first gain is adjusted to make the reference signal equal to the target value, and the second gain is adjusted to maintain a ratio of the second gain to the first gain.

摘要翻译： 提供混合模式宽范围乘法器和方法，用于将第一信号乘以第二信号以产生输出信号。 根据第一增益和参考值生成参考信号，根据第二增益生成输出信号，并且根据第二信号生成目标值，调整第一增益以使参考信号 信号等于目标值，并且调整第二增益以保持第二增益与第一增益的比率。

公开(公告)号：US07501805B2

公开(公告)日：2009-03-10

申请号：US11487388

申请日：2006-07-17

申请人： Isaac Y. Chen ,  An-Tung Chen ,  Liang-Pin Tai

发明人： Isaac Y. Chen ,  An-Tung Chen ,  Liang-Pin Tai

IPC分类号： H02M3/158

CPC分类号： H02M1/36 ,  H02M3/156 ,  H02M2001/0025 ,  Y10S323/901

摘要： A circuit and method for soft start of a system compare a feedback signal produced from an output voltage of the system with a ramp signal to generate a comparison signal, and enables the system once the comparison signal indicating the ramp signal reaches the feedback signal, such that the output voltage becomes active from a residual voltage toward a target level.

摘要翻译： 用于软启动的系统的电路和方法将从系统的输出电压产生的反馈信号与斜坡信号进行比较，以产生比较信号，并且一旦指示斜坡信号的比较信号达到反馈信号，使能系统， 输出电压从残余电压向目标电平变为有效。