公开(公告)号：US08390068B2

公开(公告)日：2013-03-05

申请号：US13361051

申请日：2012-01-30

Applicant: Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

Inventor： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

IPC: H01L27/01 ,  H01L29/74 ,  H01L23/62

CPC classification number: H01L29/7436 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

Abstract: A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract translation: 包括硅控制整流器的集成电路的硅控制整流器和静电放电保护装置。 硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。

公开(公告)号：US08299533B2

公开(公告)日：2012-10-30

申请号：US12954155

申请日：2010-11-24

Applicant: John B. Campi, Jr. ,  Shunhua Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

Inventor： John B. Campi, Jr. ,  Shunhua Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

IPC: H01L23/62

CPC classification number: H01L29/74 ,  H01L21/823892 ,  H01L27/0262 ,  H01L27/0928 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.

Abstract translation: 使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。 垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。 也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

公开(公告)号：US20120216945A1

公开(公告)日：2012-08-30

申请号：US13035420

申请日：2011-02-25

Applicant: Tao Xie ,  Junjun Li ,  Maria T. Dekimpe

Inventor： Tao Xie ,  Junjun Li ,  Maria T. Dekimpe

IPC: B32B37/18 ,  B32B38/00

CPC classification number: B32B37/144 ,  B29C61/02 ,  B29C61/06 ,  B32B2307/736

Abstract: Methods of creating reversible and irreversible wrinkle structures are provided. A shape memory polymer is heated to a transition temperature and cooled while applying a first force. A rigid film layer is secured to the shape memory polymer to form a bilayer. The original shape of the shape memory polymer is recovered to create a first set of wrinkles in the rigid film layer. The bilayer is heated to the transition temperature and a second tensile force is applied to create a second set of wrinkles in the rigid film layer.

Abstract translation: 提供了产生可逆和不可逆皱纹结构的方法。 将形状记忆聚合物加热至转变温度并在施加第一力时冷却。 刚性膜层固定在形状记忆聚合物上以形成双层。 恢复形状记忆聚合物的原始形状以在刚性膜层中产生第一组褶皱。 将双层加热至转变温度，并施加第二张力以在刚性膜层中产生第二组褶皱。

公开(公告)号：US20120181608A1

公开(公告)日：2012-07-19

申请号：US13005560

申请日：2011-01-13

Applicant: Michel J. ABOU-KHALIL ,  Robert J. GAUTHIER, JR. ,  Tom C. LEE ,  Junjun LI ,  Souvick MITRA ,  Christopher S. PUTNAM

Inventor： Michel J. ABOU-KHALIL ,  Robert J. GAUTHIER, JR. ,  Tom C. LEE ,  Junjun LI ,  Souvick MITRA ,  Christopher S. PUTNAM

IPC: H01L27/12 ,  H01L21/336

CPC classification number: H01L29/0688 ,  H01L27/0266 ,  H01L29/0615 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78696

Abstract: A method of forming a semiconductor structure, including forming a channel in a first portion of a semiconductor layer and forming a doped extension region in a second portion of the semiconductor layer abutting the channel on a first side and abutting an insulator material on a bottom side. The first portion of the semiconductor layer is thicker than the second portion of the semiconductor layer.

Abstract translation: 一种形成半导体结构的方法，包括在半导体层的第一部分中形成沟道并且在半导体层的第二部分中形成掺杂的延伸区域，所述第二部分邻近第一侧的沟道并且邻接底部的绝缘体材料 。 半导体层的第一部分比半导体层的第二部分厚。

公开(公告)号：US20120146150A1

公开(公告)日：2012-06-14

申请号：US12967114

申请日：2010-12-14

Applicant: Robert J. Gauthier, JR. ,  Mahender Kumar ,  Junjun Li ,  Dustin K. Slisher

Inventor： Robert J. Gauthier, JR. ,  Mahender Kumar ,  Junjun Li ,  Dustin K. Slisher

IPC: H01L23/62 ,  H01L21/336

CPC classification number: H01L23/60 ,  H01L27/0266 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.

Abstract translation: 公开了自保护静电放电场效应晶体管（SPESDFET）的实施例。 在SPESDFET实施例中，电阻区域横向定位在深源极/漏极区域的两个离散部分之间：与沟道区域相邻的第一部分和接触的第二部分。 深源极/漏极区域的第二部分被硅化，但是与沟道区域和电阻区域相邻的第一部分是非硅化的。 另外，栅极结构可以是硅化的或非硅化的。 利用这种配置，所公开的SPESDFET提供强大的ESD保护，而不消耗额外的面积，而不改变基本FET设计（例如，不增加深源/漏区和沟道区之间的距离）。 还公开了将SPESDFET作为输入/输出（I / O）焊盘驱动器和用于形成SPESDFET和集成电路的方法实施例的集成电路的实施例。

公开(公告)号：US20120126285A1

公开(公告)日：2012-05-24

申请号：US12954155

申请日：2010-11-24

Applicant: John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

Inventor： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

IPC: H01L29/74 ,  G06F17/50 ,  H01L21/332

CPC classification number: H01L29/74 ,  H01L21/823892 ,  H01L27/0262 ,  H01L27/0928 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.

Abstract translation: 使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。 垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。 也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

公开(公告)号：US08039868B2

公开(公告)日：2011-10-18

申请号：US12342228

申请日：2008-12-23

Applicant: Robert J. Gauthier, Jr. ,  Junjun Li ,  Aniket Srivastava

Inventor： Robert J. Gauthier, Jr. ,  Junjun Li ,  Aniket Srivastava

IPC: H01L29/72 ,  H01L29/74

CPC classification number: H01L29/66386 ,  H01L24/06 ,  H01L27/0262 ,  H01L29/74 ,  H01L29/7436 ,  H01L2224/05554 ,  H01L2924/14 ,  H01L2924/00

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. Further, the first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.

Abstract translation: 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括形成在衬底中的第一和第二可控硅整流器（SCR）。 此外，第一和第二SCR各自包括在第一和第二SCR之间共同共享的至少一个部件。

公开(公告)号：US07968908B2

公开(公告)日：2011-06-28

申请号：US12563610

申请日：2009-09-21

Applicant: Michel J. Abou-Khalil ,  Robert Gauthier ,  Junjun Li

Inventor： Michel J. Abou-Khalil ,  Robert Gauthier ,  Junjun Li

IPC: H01L29/73

CPC classification number: H01L23/60 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: Semiconductor structures providing protection against electrostatic events of both polarities are provided. A pair of p-n junctions is provided underneath a shallow trench isolation portion between a first-conductivity-type well and each of a signal-side second-conductivity-type well and an electrical-ground-side second-conductivity-type well in a semiconductor substrate. A second-conductivity-type doped region and a first-conductivity-type doped region are formed above each second-conductivity-type well such that a portion of the second-conductivity-type well resistively separates the second-conductivity-type doped region and the first-conductivity-type doped region within the semiconductor substrate. Each of the second-conductivity-type doped regions is wired either to a signal node or electrical ground. One of the two npn transistors and one of the two p-n diodes, each inherently present in the semiconductor structure, turn on to provide protection against electrical discharge events involving either type of excessive electrical charges.

Abstract translation: 提供了提供两极性静电事件保护的半导体结构。 在第一导电型阱与信号侧第二导电型阱和电 - 接地侧第二导电型阱中的每一个之间的浅沟槽隔离部分的半导体中设置一对pn结 基质。 第二导电型掺杂区域和第一导电型掺杂区域形成在每个第二导电型阱之上，使得第二导电型阱的一部分阱电阻地分离第二导电型掺杂区域，以及 半导体衬底内的第一导电型掺杂区域。 每个第二导电类型的掺杂区域被连接到信号节点或电接地。 两个npn晶体管中的一个和两个固有地存在于半导体结构中的两个p-n二极管中的一个导通以提供防止涉及任何一种过量电荷的放电事件的保护。

公开(公告)号：US20110147794A1

公开(公告)日：2011-06-23

申请号：US13035549

申请日：2011-02-25

Applicant: Robert J. GAUTHIER, JR. ,  Junjun LI ,  Souvick MITRA

Inventor： Robert J. GAUTHIER, JR. ,  Junjun LI ,  Souvick MITRA

IPC: H01L29/74

CPC classification number: H01L29/7436 ,  H01L27/0259 ,  H01L29/861

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.

Abstract translation: 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括一个P + -N体二极管和一个N + -P体二极管。 P + -N体二极管和N + -P体二极管横向集成。

公开(公告)号：US20110068364A1

公开(公告)日：2011-03-24

申请号：US12563610

申请日：2009-09-21

Applicant: Michel J. Abou-Khalil ,  Robert Gauthier ,  Junjun Li

Inventor： Michel J. Abou-Khalil ,  Robert Gauthier ,  Junjun Li

IPC: H01L23/60

CPC classification number: H01L23/60 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: Semiconductor structures providing protection against electrostatic events of both polarities are provided. A pair of p-n junctions is provided underneath a shallow trench isolation portion between a first-conductivity-type well and each of a signal-side second-conductivity-type well and an electrical-ground-side second-conductivity-type well in a semiconductor substrate. A second-conductivity-type doped region and a first-conductivity-type doped region are formed above each second-conductivity-type well such that a portion of the second-conductivity-type well resistively separates the second-conductivity-type doped region and the first-conductivity-type doped region within the semiconductor substrate. Each of the second-conductivity-type doped regions is wired either to a signal node or electrical ground. One of the two npn transistors and one of the two p-n diodes, each inherently present in the semiconductor structure, turn on to provide protection against electrical discharge events involving either type of excessive electrical charges.

Abstract translation: 提供了提供两极性静电事件保护的半导体结构。 在第一导电型阱与信号侧第二导电型阱和电 - 接地侧第二导电型阱中的每一个之间的浅沟槽隔离部分的半导体中设置一对pn结 基质。 第二导电型掺杂区域和第一导电型掺杂区域形成在每个第二导电型阱之上，使得第二导电型阱的一部分阱电阻地分离第二导电型掺杂区域和 半导体衬底内的第一导电型掺杂区域。 每个第二导电类型的掺杂区域被连接到信号节点或电接地。 两个npn晶体管中的一个和两个固有地存在于半导体结构中的两个p-n二极管中的一个导通以提供防止涉及任何一种过量电荷的放电事件的保护。