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    Self-protected electrostatic discharge field effect transistor (SPESDFET), an integrated circuit incorporating the SPESDFET as an input/output (I/O) pad driver and associated methods of forming the SPESDFET and the integrated circuit
    1.
    发明授权
    Self-protected electrostatic discharge field effect transistor (SPESDFET), an integrated circuit incorporating the SPESDFET as an input/output (I/O) pad driver and associated methods of forming the SPESDFET and the integrated circuit 有权
    自保护静电放电场效应晶体管（SPESDFET），一种集成了SPESDFET作为输入/输出（I / O）焊盘驱动器的集成电路，以及形成SPESDFET和集成电路的相关方法

    公开(公告)号：US08610217B2

    公开(公告)日：2013-12-17

    申请号：US12967114

    申请日：2010-12-14

    申请人： Robert J. Gauthier, Jr. ,  Mahender Kumar ,  Junjun Li ,  Dustin K. Slisher

    发明人： Robert J. Gauthier, Jr. ,  Mahender Kumar ,  Junjun Li ,  Dustin K. Slisher

    IPC分类号： H01L23/62

    CPC分类号： H01L23/60 ,  H01L27/0266 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.

    摘要翻译： 公开了自保护静电放电场效应晶体管（SPESDFET）的实施例。 在SPESDFET实施例中，电阻区域横向定位在深源极/漏极区域的两个离散部分之间：与沟道区域相邻的第一部分和接触的第二部分。 深源极/漏极区域的第二部分被硅化，但是与沟道区域和电阻区域相邻的第一部分是非硅化的。 另外，栅极结构可以是硅化的或非硅化的。 利用这种配置，所公开的SPESDFET提供强大的ESD保护，而不消耗额外的面积，而不改变基本FET设计（例如，不增加深源/漏区和沟道区之间的距离）。 还公开了将SPESDFET作为输入/输出（I / O）焊盘驱动器和用于形成SPESDFET和集成电路的方法实施例的集成电路的实施例。

    SELF-PROTECTED ELECTROSTATIC DISCHARGE FIELD EFFECT TRANSISTOR (SPESDFET), AN INTEGRATED CIRCUIT INCORPORATING THE SPESDFET AS AN INPUT/OUTPUT (I/O) PAD DRIVER AND ASSOCIATED METHODS OF FORMING THE SPESDFET AND THE INTEGRATED CIRCUIT
    2.
    发明申请
    SELF-PROTECTED ELECTROSTATIC DISCHARGE FIELD EFFECT TRANSISTOR (SPESDFET), AN INTEGRATED CIRCUIT INCORPORATING THE SPESDFET AS AN INPUT/OUTPUT (I/O) PAD DRIVER AND ASSOCIATED METHODS OF FORMING THE SPESDFET AND THE INTEGRATED CIRCUIT 有权
    自保护静电放电场效应晶体管（SPESDFET），集成电路作为输入/输出（I / O）PAD驱动器的SPESDFET和相关的形成SPESDFET和集成电路的方法

    公开(公告)号：US20120146150A1

    公开(公告)日：2012-06-14

    申请号：US12967114

    申请日：2010-12-14

    申请人： Robert J. Gauthier, JR. ,  Mahender Kumar ,  Junjun Li ,  Dustin K. Slisher

    发明人： Robert J. Gauthier, JR. ,  Mahender Kumar ,  Junjun Li ,  Dustin K. Slisher

    IPC分类号： H01L23/62 ,  H01L21/336

    CPC分类号： H01L23/60 ,  H01L27/0266 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.

    摘要翻译： 公开了自保护静电放电场效应晶体管（SPESDFET）的实施例。 在SPESDFET实施例中，电阻区域横向定位在深源极/漏极区域的两个离散部分之间：与沟道区域相邻的第一部分和接触的第二部分。 深源极/漏极区域的第二部分被硅化，但是与沟道区域和电阻区域相邻的第一部分是非硅化的。 另外，栅极结构可以是硅化的或非硅化的。 利用这种配置，所公开的SPESDFET提供强大的ESD保护，而不消耗额外的面积，而不改变基本FET设计（例如，不增加深源/漏区和沟道区之间的距离）。 还公开了将SPESDFET作为输入/输出（I / O）焊盘驱动器和用于形成SPESDFET和集成电路的方法实施例的集成电路的实施例。

    EDRAM including metal plates
    3.
    发明授权
    EDRAM including metal plates 有权
    EDRAM包括金属板

    公开(公告)号：US07943474B2

    公开(公告)日：2011-05-17

    申请号：US12391631

    申请日：2009-02-24

    申请人： Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Mahender Kumar

    发明人： Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Mahender Kumar

    IPC分类号： H01L21/20

    CPC分类号： H01L29/66181 ,  H01L28/91

    摘要： A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode.An upper electrode is then formed on the conformal dielectric layer. The forming of the upper electrode may include a conformal deposition of metal nitride layer, and a non-conformal deposition of an electrically conductive material atop the metal nitride layer, in which the electrically conductive material encloses the at least one trench.

    摘要翻译： 通过首先在半导体衬底中形成至少一个沟槽来提供形成存储器件的方法。 接下来，在至少一个沟槽中形成下电极，之后在下电极上形成保形电介质层。 然后在保形电介质层上形成上电极。 上电极的形成可以包括金属氮化物层的共形沉积，以及金属氮化物层顶部的导电材料的非共形沉积，其中导电材料包围至少一个沟槽。

    Dual metal gate finFETs with single or dual high-K gate dielectric
    4.
    发明授权
    Dual metal gate finFETs with single or dual high-K gate dielectric 有权
    具有单或双高K栅极电介质的双金属栅极finFET

    公开(公告)号：US07659157B2

    公开(公告)日：2010-02-09

    申请号：US11860840

    申请日：2007-09-25

    申请人： Brian J. Greene ,  Mahender Kumar

    发明人： Brian J. Greene ,  Mahender Kumar

    IPC分类号： H01L21/8238 ,  H01L21/8222

    CPC分类号： H01L27/1211 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/7851

    摘要： A first high-k gate dielectric layer and a first metal gate layer are formed on first and second semiconductor fins. A first metal gate ring is formed on the first semiconductor fin. In one embodiment, the first high-k gate dielectric layer remains on the second semiconductor fin. A second metal gate layer and a silicon containing layer are deposited and patterned to form gate electrodes. In another embodiment, a second high-k dielectric layer replaces the first high-k dielectric layer over the second semiconductor fin, followed by formation of a second metal gate layer. A first electrode comprising a first gate dielectric and a first metal gate is formed on the first semiconductor fin, while a second electrode comprising a second gate dielectric and a second metal gate is formed on the second semiconductor fin. Absence of high-k gate dielectric materials on a gate wiring prevents increase in parasitic resistance.

    摘要翻译： 在第一和第二半导体鳍片上形成第一高k栅介质层和第一金属栅极层。 第一金属栅环形成在第一半导体鳍上。 在一个实施例中，第一高k栅介质层保留在第二半导体鳍片上。 沉积第二金属栅极层和含硅层以形成栅电极。 在另一个实施例中，第二高k电介质层替代第二半导体鳍片上的第一高k电介质层，随后形成第二金属栅极层。 包括第一栅极电介质和第一金属栅极的第一电极形成在第一半导体鳍片上，而在第二半导体鳍片上形成包括第二栅极电介质和第二金属栅极的第二电极。 在栅极布线上缺少高k栅极电介质材料可防止寄生电阻的增加。

    PERFORMANCE ENHANCEMENT ON BOTH NMOSFET AND PMOSFET USING SELF-ALIGNED DUAL STRESSED FILMS
    6.
    发明申请
    PERFORMANCE ENHANCEMENT ON BOTH NMOSFET AND PMOSFET USING SELF-ALIGNED DUAL STRESSED FILMS 审中-公开
    使用自对准双应力膜的两个NMOSFET和PMOSFET的性能增强

    公开(公告)号：US20080169510A1

    公开(公告)日：2008-07-17

    申请号：US11623871

    申请日：2007-01-17

    申请人： Mahender Kumar ,  Huilong Zhu

    发明人： Mahender Kumar ,  Huilong Zhu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L27/088 ,  H01L27/092 ,  H01L29/7843

    摘要： In an integrated circuit comprising both PMOSFETs and NMOSFETs, carrier mobility is enhanced on both types of FETs using dual stressed films. The adverse impact of having both layers of stressed films along the boundary between different types of films is eliminated by utilizing self-alignment of the edges of a second stressed film to a preexisting edge of a first stressed film. At the boundary between the two stressed films, one stressed film abuts another but no stressed film overlies another stressed film. By avoiding any overlap of stressed films, the stress exerted on the MOSFET channels is maximized.

    摘要翻译： 在包括PMOSFET和NMOSFET的集成电路中，使用双应力膜的两种类型的FET都增加了载流子迁移率。 通过利用第二应力膜的边缘对第一应力膜的预先存在的边缘进行自对准，消除了沿不同类型的膜之间的边界具有两层应力膜的不利影响。 在两个应力薄膜之间的边界处，一个应力薄膜邻接另一个，但没有应力薄膜覆盖另一个应力薄膜。 通过避免应力膜的任何重叠，施加在MOSFET通道上的应力最大化。

    STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICON REGIONS
    7.
    发明申请
    STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICON REGIONS 有权
    在半导体器件中的STI形成，包括SOI和块状硅区域

    公开(公告)号：US20060244093A1

    公开(公告)日：2006-11-02

    申请号：US11425467

    申请日：2006-06-21

    申请人： Michael Steigerwalt ,  Mahender Kumar ,  Herbert Ho ,  David Dobuzinsky ,  Johnathan Faltermeier ,  Denise Pendleton

    发明人： Michael Steigerwalt ,  Mahender Kumar ,  Herbert Ho ,  David Dobuzinsky ,  Johnathan Faltermeier ,  Denise Pendleton

    IPC分类号： H01L29/00

    CPC分类号： H01L21/7624 ,  H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

    摘要： Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

    摘要翻译： 公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。 可以通过使用STI掩模蚀刻到最上层的硅层，在SOI和体硅区域中同时蚀刻STI，进行蚀刻到体硅区域中期望的深度并停止在SOI区域的埋入绝缘体上的定时蚀刻 ，并蚀刻穿过SOI区域的埋层绝缘体。 用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。 此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。 本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

    Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof
    8.
    发明申请
    Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof 有权
    具有用于低衬底偏置操作的薄埋氧化物（BOX）上的反向集电极的超薄SOI垂直双极晶体管及其方法

    公开(公告)号：US20050184360A1

    公开(公告)日：2005-08-25

    申请号：US10787002

    申请日：2004-02-25

    申请人： Herbert Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul Papworth ,  Christopher Sheraw ,  Michael Steigerwalt

    发明人： Herbert Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul Papworth ,  Christopher Sheraw ,  Michael Steigerwalt

    IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08 ,  H01L27/082 ,  H01L27/12 ,  H01L29/73 ,  H01L29/732

    CPC分类号： H01L29/7317

    摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

    摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

    Structures, fabrication methods, design structures for strained fin field effect transistors (FinFets)
    9.
    发明授权
    Structures, fabrication methods, design structures for strained fin field effect transistors (FinFets) 有权
    应变鳍场效应晶体管的结构，制造方法，设计结构（FinFets）

    公开(公告)号：US08053838B2

    公开(公告)日：2011-11-08

    申请号：US12146728

    申请日：2008-06-26

    申请人： Xiaomeng Chen ,  Byeong Yeol Kim ,  Mahender Kumar ,  Huilong Zhu

    发明人： Xiaomeng Chen ,  Byeong Yeol Kim ,  Mahender Kumar ,  Huilong Zhu

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01L29/7848 ,  H01L29/66795 ,  H01L29/785

    摘要： A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain creating fin region. The first semiconductor seed region is sandwiched between the first strain creating fin region and the dielectric layer. The first semiconductor seed region includes a first semiconductor material. The first strain creating fin region includes the first semiconductor material and a second semiconductor material different than the first semiconductor material. A first atom percent of the first semiconductor material in the first semiconductor seed region is different than a second atom percent of the first semiconductor material in the first strain creating fin region.

    摘要翻译： FinFet的半导体结构，制造方法和设计结构。 FinFet包括电介质层，电介质层上的中央半导体鳍片区域，电介质层上的第一半导体种子区域和第一应变产生鳍片区域。 第一半导体种子区域夹在第一应变产生鳍区域和电介质层之间。 第一半导体种子区域包括第一半导体材料。 第一应变产生鳍区域包括第一半导体材料和与第一半导体材料不同的第二半导体材料。 第一半导体晶种区域中的第一半导体材料的第一原子百分比不同于第一应变产生鳍区域中的第一半导体材料的第二原子百分比。