公开(公告)号：US06291288B1

公开(公告)日：2001-09-18

申请号：US09292537

申请日：1999-04-15

Applicant: Kuo-Tai Huang ,  Tri-Rung Yew

Inventor： Kuo-Tai Huang ,  Tri-Rung Yew

IPC: H01L218242

CPC classification number: H01L28/40 ,  H01L21/31111 ,  H01L21/3144 ,  H01L21/3185 ,  H01L21/3211 ,  H01L27/1085

Abstract: A semiconductor fabrication method is provided for the fabrication of a dielectric structure for a storage capacitor in dynamic random-access memory (DRAM). In particular, the resultant dielectric structure can be fabricated thinner and more structurally-undefective than the prior art. By the method, a first nitridation process is performed to form a dielectric layer over a bottom electrode. Next, a layer of silicon nitride is formed over the dielectric layer. This silicon nitride layer would be typically formed with an undesired rugged surface with many punctures. To eliminate this structural defect, a second nitridation process is performed on the silicon nitride layer. The resultant silicon nitride layer and the dielectric layer in combination constitute an ON structure serving as the intended dielectric structure. Alternatively, an oxide layer can be further formed over the silicon nitride layer to constitute an ONO structure serving as the intended dielectric structure. The second nitridation process can be carried out either through a rapid thermal treatment process with the use of nitrogen, ammonia, or a mixture of nitrogen and ammonia; or alternatively through a nitrogen plasma treatment process.

Abstract translation: 提供了用于制造用于动态随机存取存储器（DRAM）中的存储电容器的电介质结构的半导体制造方法。 特别地，所制成的电介质结构可以制造得比现有技术更薄且更结构上不有效。 通过该方法，进行第一次氮化处理以在底部电极上形成电介质层。 接下来，在电介质层上形成氮化硅层。 该氮化硅层通常形成有具有许多穿孔的不期望的粗糙表面。 为了消除这种结构缺陷，对氮化硅层进行第二次氮化处理。 所得到的氮化硅层和电介质层组合构成用作预期电介质结构的ON结构。 或者，可以在氮化硅层上进一步形成氧化物层，以构成用作预期电介质结构的ONO结构。 第二次氮化处理可以通过使用氮，氨或氮和氨的混合物的快速热处理方法进行; 或者通过氮等离子体处理工艺。

公开(公告)号：US06174765B1

公开(公告)日：2001-01-16

申请号：US09010005

申请日：1998-01-21

Applicant: Wen-Yi Hsieh ,  Kuo-Tai Huang

Inventor： Wen-Yi Hsieh ,  Kuo-Tai Huang

IPC: H01L218242

CPC classification number: H01L28/55 ,  H01L21/31691 ,  H01L27/1085

Abstract: A method of reducing the leakage current of a dielectric layer of a capacitor. A substrate having a dielectric layer formed thereon is disposed into a furnace. A first annealing step is performed for nucleation. A second annealing step is performed to control the number of the nuclei. A third annealing step is performed for grain growth.

Abstract translation: 一种降低电容器的电介质层的漏电流的方法。 将其上形成有电介质层的基板设置在炉中。 进行成核的第一退火步骤。 执行第二退火步骤以控制核的数量。 进行晶粒生长的第三退火步骤。

公开(公告)号：US6083789A

公开(公告)日：2000-07-04

申请号：US60323

申请日：1998-04-14

Applicant: Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

Inventor： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L27/10852 ,  H01L28/91

Abstract: A method for forming a DRAM capacitor whose titanium nitride electrode is fabricated in a sequence of steps that results in a good step-coverage. Moreover, contamination of the titanium nitride layer and cross-diffusion between the titanium nitride layer and the dielectric film layer is reduced to a minimum. The method of forming the titanium nitride layer includes the steps of depositing a first titanium nitride layer over a dielectric film layer using a conventional physical vapor deposition process. Then, a second titanium nitride layer is deposited over the first titanium nitride layer using a collimated physical vapor deposition process.

Abstract translation: 一种形成DRAM电容器的方法，其中氮化钛电极以一系列步骤制造，这导致良好的阶梯覆盖。 此外，氮化钛层的污染和氮化钛层与电介质膜层之间的交叉扩散减少到最小。 形成氮化钛层的方法包括以下步骤：使用常规的物理气相沉积工艺在电介质膜层上沉积第一氮化钛层。 然后，使用准直的物理气相沉积工艺在第一氮化钛层上沉积第二氮化钛层。

公开(公告)号：US6057189A

公开(公告)日：2000-05-02

申请号：US24183

申请日：1998-02-17

Applicant: Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Wen-Kuan Yeh ,  Tri-Rung Yew

Inventor： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Wen-Kuan Yeh ,  Tri-Rung Yew

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/822 ,  H01L21/8242

CPC classification number: H01L28/40 ,  Y10S438/964

Abstract: A method of fabricating a capacitor, comprising the steps of: providing a conductive layer over a semiconductor substrate having a transistor formed thereon to connect a source/drain region of the transistor; forming a hemispherical grained silicon layer over the conductive layer; using an implantation method to implant ions into the hemispherical grained silicon layer; performing a thermal treatment process to convert the ions into a barrier layer over the hemispherical grained silicon layer; performing a wet etching process to clean a surface of the barrier layer; forming a dielectric layer over the barrier layer and forming a top electrode over the dielectric layer.

Abstract translation: 一种制造电容器的方法，包括以下步骤：在其上形成有晶体管的半导体衬底上提供导电层以连接晶体管的源极/漏极区域; 在所述导电层上形成半球形晶粒硅层; 使用植入方法将离子注入到半球形晶粒硅层中; 执行热处理工艺以将离子转换成半球形晶粒硅层上的阻挡层; 执行湿蚀刻工艺以清洁阻挡层的表面; 在阻挡层上形成电介质层，并在电介质层上形成顶部电极。

公开(公告)号：US5994183A

公开(公告)日：1999-11-30

申请号：US996696

申请日：1997-12-23

Applicant: Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

Inventor： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L21/28518 ,  H01L27/10852

Abstract: A method for forming a high capacitance charge storage structure that can be applied to a substrate wafer having MOS transistor already formed thereon. The method is to form an insulating layer above the substrate wafer. Next, a contact window exposing a source/drain region is formed in the insulating layer. Then, a tungsten suicide layer, which functions as a lower electrode for the charge storage structure, is formed over the substrate. Thereafter, a tungsten nitride layer is formed over the tungsten silicide layer, and then a dielectric layer is formed over the tungsten nitride layer. The dielectric layer is preferably a tantalum oxide layer. Finally, a titanium nitride layer, which functions as an upper electrode for the charge storage structure, is formed over the tantalum oxide layer.

Abstract translation: 一种用于形成可以应用于已经形成有MOS晶体管的衬底晶片的高电容电荷存储结构的方法。 该方法是在衬底晶片之上形成绝缘层。 接下来，在绝缘层中形成暴露源极/漏极区域的接触窗口。 然后，在基板上形成用作电荷存储结构的下电极的硅化钨层。 此后，在硅化钨层之上形成氮化钨层，然后在氮化钨层上形成电介质层。 电介质层优选为氧化钽层。 最后，在钽氧化物层上形成用作电荷存储结构的上电极的氮化钛层。

公开(公告)号：US5895254A

公开(公告)日：1999-04-20

申请号：US993500

申请日：1997-12-18

Applicant: Kuo-Tai Huang ,  Tony Lin ,  Water Lur

Inventor： Kuo-Tai Huang ,  Tony Lin ,  Water Lur

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224 ,  Y10S148/05

Abstract: A method for forming a shallow trench isolation structure comprising the steps of sequentially forming a pad oxide layer and a mask layer over a substrate, then patterning the mask layer and the pad oxide layer. Next, an opening is formed in the mask layer, wherein the sidewall of the opening in the mask layer forms a sharp angle with the substrate layer below. Thereafter, the substrate is etched from the opening down to form a trench. In a subsequent step, insulating material is deposited into the trench forming an insulating layer rising to a level higher than the mask layer, and accompanying by the formation of a protuberance at the side of the insulating layer. Subsequently, the mask layer is removed, and then portions of the pad oxide layer is removed to form a spacer on the upper side of the insulating layer. Finally, the pad oxide layer above the substrate is removed to complete the formation of the shallow trench isolation structure. Due to the presence of a spacer, resistance against subsequent etching is increased at the junction between the trench insulating layer and the substrate layer. Thus, kink effect caused by the over-etching of the insulating layer is prevented.

Abstract translation: 一种用于形成浅沟槽隔离结构的方法，包括以下步骤：在衬底上顺序形成焊盘氧化物层和掩模层，然后对掩模层和焊盘氧化物层进行图案化。 接下来，在掩模层中形成开口，其中掩模层中的开口的侧壁与下面的基底层形成锐角。 此后，从开口向下蚀刻衬底以形成沟槽。 在随后的步骤中，将绝缘材料沉积到沟槽中，形成上升到高于掩模层的水平的绝缘层，并伴随着在绝缘层一侧形成突起。 随后，去除掩模层，然后去除焊盘氧化物层的一部分，以在绝缘层的上侧形成间隔物。 最后，去除衬底上方的衬垫氧化物层以完成浅沟槽隔离结构的形成。 由于存在间隔物，在沟槽绝缘层和衬底层之间的结处增加了对后续蚀刻的抵抗力。 因此，防止了由绝缘层的过度蚀刻引起的扭结效应。

公开(公告)号：USD371289S

公开(公告)日：1996-07-02

申请号：US038397

申请日：1995-05-04

Applicant: Kuo-Tai Huang

Designer： Kuo-Tai Huang