公开(公告)号：US09721840B2

公开(公告)日：2017-08-01

申请号：US15194577

申请日：2016-06-28

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Ming Lai ,  Chien-Chung Huang ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L21/283 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/823437 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/3211 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

公开(公告)号：US20160307805A1

公开(公告)日：2016-10-20

申请号：US15194577

申请日：2016-06-28

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Ming Lai ,  Chien-Chung Huang ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC分类号： H01L21/8234 ,  H01L21/3213 ,  H01L21/283 ,  H01L21/321

CPC分类号： H01L21/823437 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/3211 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

摘要翻译： 本发明提供一种互补金属氧化物半导体器件，其包括PMOS和NMOS。 PMOS具有P型金属栅极，其包括底部阻挡层，P功函数金属（PWFM）层，N功函数调整（NWFT）层，N功函数金属（NWFM）层和金属层。 NMOS具有N型金属栅极，其包括NWFT层，NWFM层和低电阻层。 本发明还提供一种形成该方法的方法。

公开(公告)号：US20160172191A1

公开(公告)日：2016-06-16

申请号：US15042648

申请日：2016-02-12

申请人： Hitachi Kokusai Electric Inc.

发明人： Akito HIRANO

IPC分类号： H01L21/02

CPC分类号： H01L21/02332 ,  H01J37/32082 ,  H01J37/32669 ,  H01L21/02068 ,  H01L21/02247 ,  H01L21/28273 ,  H01L21/3211 ,  H01L21/67109 ,  H01L21/67115 ,  H01L27/11517

摘要： There are provided a substrate processing apparatus including: a process chamber accommodating a substrate including a polysilicon film having an oxygen-containing layer formed thereon; a heating unit installed in the process chamber to heat the substrate; a gas supply unit configured to supply a process gas containing nitrogen and hydrogen to the substrate in the process chamber; an excitation unit configured to excite the process gas supplied into the process chamber; an exhaust unit configured to exhaust an inside of the process chamber; and a control unit configured to control at least the heating unit, the gas supply unit, the excitation unit and the exhaust unit so as to modify the oxygen-containing layer into an oxynitride layer or a nitride layer by heating the substrate to a predetermined temperature using the heating unit, exciting the process gas supplied by the gas supply unit using the excitation unit, and supplying the process gas excited by the excitation unit to the substrate.

摘要翻译： 提供了一种基板处理设备，包括：处理室，其容纳包括其上形成有含氧层的多晶硅膜的基板; 加热单元，其安装在所述处理室中以加热所述基板; 气体供给单元，其构造成在所述处理室中向所述基板供给含有氮和氢的处理气体; 激励单元，被配置为激励供给到所述处理室中的处理气体; 排气单元，构造成排出处理室的内部; 以及控制单元，被配置为至少控制所述加热单元，所述气体供应单元，所述激励单元和所述排气单元，以通过将所述基板加热到预定温度来将所述含氧层改性为氮氧化物层或氮化物层 使用加热单元，使用激励单元激励由气体供应单元供应的处理气体，并将由激励单元激发的处理气体供应到基板。

公开(公告)号：US20160163782A1

公开(公告)日：2016-06-09

申请号：US15008619

申请日：2016-01-28

申请人： Texas Instruments Incorporated

发明人： John Paul CAMPBELL ,  Kaiping LIU

IPC分类号： H01L49/02 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/027

CPC分类号： H01L28/60 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02301 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/0273 ,  H01L21/28035 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/3211 ,  H01L21/32133 ,  H01L21/32139 ,  H01L27/0629

摘要： A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric.

摘要翻译： 形成集成电路的工艺形成具有金属表面的高精度电容器底板，并执行金属表面的等离子体处理。 通过在第一层为氮化硅的高精度电容器底板上沉积电容器电介质的第一层而形成高精度电容器电介质，在第一层上沉积第二层电容器电介质，其中第二部分是二氧化硅 并且在第二部分上沉积电容器电介质的第三层，其中第三层是氮化硅。 也可以在电容器电介质预沉积和/或沉积后的层上进行等离子体处理。 在高精度电容器电介质上形成金属高精度电容器顶板。

公开(公告)号：US08940615B2

公开(公告)日：2015-01-27

申请号：US13607798

申请日：2012-09-09

申请人： Te-Lin Sun ,  Chien-Liang Lin ,  Yu-Ren Wang

发明人： Te-Lin Sun ,  Chien-Liang Lin ,  Yu-Ren Wang

IPC分类号： H01L21/76 ,  H01L21/31

CPC分类号： H01L21/76232 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/3211 ,  H01L21/76237 ,  H01L29/7846

摘要： The present invention provides a method of forming an isolation structure. A substrate is provided, and a trench is formed in the substrate. Next, a semiconductor layer is formed on a surface of the trench. A nitridation is carried out to form a nitridation layer in the semiconductor layer. Lastly, an insulation layer is filled into the trench.

摘要翻译： 本发明提供一种形成隔离结构的方法。 提供衬底，并且在衬底中形成沟槽。 接下来，在沟槽的表面上形成半导体层。 进行氮化，以在半导体层中形成氮化层。 最后，将绝缘层填充到沟槽中。

公开(公告)号：US20140273518A1

公开(公告)日：2014-09-18

申请号：US14204819

申请日：2014-03-11

申请人： APPLIED MATERIALS, INC.

发明人： MATTHEW S. ROGERS ,  KEVIN BAUTISTA

IPC分类号： C23C16/52 ,  C23C16/455 ,  C23C16/458 ,  H01L21/02

CPC分类号： C23C16/52 ,  C23C16/045 ,  C23C16/452 ,  C23C16/45502 ,  C23C16/4584 ,  H01L21/02057 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/3211

摘要： Methods of forming a layer on a substrate may include providing a substrate to a process chamber, the process chamber having a gas port, an exhaust, and a plasma port disposed between the gas port and the exhaust; providing a process gas from the gas port in a first direction such that the process gas flows across the substrate; providing a plasma such that a flow of the plasma interacts with a flow of the process gas at an angle that is non-perpendicular; and rotating the substrate while providing the process gas and the plasma, wherein a thickness profile of the layer is controlled by adjusting at least one of a flow velocity of the process gas, a flow velocity of the plasma, the angle the flow of the plasma interacts with the flow of the process gas, or a direction of rotation of the substrate.

摘要翻译： 在基板上形成层的方法可以包括向处理室提供衬底，处理室具有设置在气体端口和排气之间的气体端口，排气口和等离子体端口; 在第一方向上从气体端口提供处理气体，使得处理气体流过基板; 提供等离子体，使得等离子体的流动与处理气体的流以非垂直的角度相互作用; 以及在提供处理气体和等离子体的同时旋转衬底，其中通过调节工艺气体的流速，等离子体的流速，等离子体的流动角度，角度等等来控制该层的厚度分布 与工艺气体的流动或衬底的旋转方向相互作用。

公开(公告)号：US08741785B2

公开(公告)日：2014-06-03

申请号：US13658594

申请日：2012-10-23

申请人： Applied Materials, Inc.

发明人： Christopher S. Olsen ,  Yoshitaka Yokota

IPC分类号： H01L21/31

CPC分类号： H01L21/02164 ,  H01J37/32357 ,  H01J37/32422 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28273 ,  H01L21/3115 ,  H01L21/3211 ,  H01L27/11524

摘要： Embodiments described herein generally relate to methods for manufacturing flash memory devices. In one embodiment, the method includes generating a plasma comprising nitrogen-containing radicals in a remote plasma applicator, flowing the plasma comprising nitrogen-containing radicals into a processing region of the processing chamber where a semiconductor device is disposed, wherein the semiconductor device has a substrate comprising an oxide layer formed thereon, exposing an exposed surface of the oxide layer to the nitrogen-containing radicals, and incorporating nitrogen in the exposed surface of the oxide layer of the substrate.

公开(公告)号：US08598580B2

公开(公告)日：2013-12-03

申请号：US13639028

申请日：2011-03-30

申请人： Yasuaki Terao ,  Shinya Morita ,  Aya Miki ,  Katsufumi Tomihisa ,  Hiroshi Goto

发明人： Yasuaki Terao ,  Shinya Morita ,  Aya Miki ,  Katsufumi Tomihisa ,  Hiroshi Goto

IPC分类号： H01L29/16

CPC分类号： H01L23/53238 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/3211 ,  H01L21/76867 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4958 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Disclosed is a wiring structure that attains excellent low-contact resistance even if eliminating a barrier metal layer that normally is disposed between a Cu alloy wiring film and a semiconductor layer, and wiring structure with excellent adhesion. The wiring structure is provided with a semiconductor layer, and a Cu alloy layer, on a substrate in this order from the substrate side. A laminated structure is included between the semiconductor layer, and the Cu alloy layer. The laminated structure is composed of a (N, C, F, O) layer which contains at least one element selected from among a group composed of nitrogen, carbon, fluorine, and oxygen, and a Cu—Si diffusion layer which includes Cu and Si, in this order from the substrate side. At least one element selected from among the group composed of nitrogen, carbon, fluorine, and oxygen that composes the (N, C, F, O) layer is bonded to Si in the semiconductor layer. The Cu alloy layer is a laminated structure containing a Cu—X alloy layer (a first layer) and a second layer.

摘要翻译： 公开了即使消除通常设置在Cu合金布线膜和半导体层之间的阻挡金属层以及具有优异的粘附性的布线结构，也可以获得优异的低接触电阻的布线结构。 布线结构在基板上依次从基板侧设置有半导体层和Cu合金层。 在半导体层和Cu合金层之间包含层叠结构。 层叠结构由含有选自氮，碳，氟和氧中的至少一种元素的（N，C，F，O）层构成，Cu-Si扩散层包含Cu和 Si，从衬底侧依次。 构成（N，C，F，O）层的由氮，碳，氟和氧构成的组中的至少一种元素与半导体层中的Si键合。 Cu合金层是含有Cu-X合金层（第一层）和第二层的层叠结构。

公开(公告)号：US20130026470A1

公开(公告)日：2013-01-31

申请号：US13639028

申请日：2011-03-30

申请人： Yasuaki Terao ,  Shinya Morita ,  Aya Miki ,  Katsufumi Tomihisa ,  Hiroshi Goto

发明人： Yasuaki Terao ,  Shinya Morita ,  Aya Miki ,  Katsufumi Tomihisa ,  Hiroshi Goto

IPC分类号： H01L29/16

CPC分类号： H01L23/53238 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/3211 ,  H01L21/76867 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4958 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Disclosed is a wiring structure that attains excellent low-contact resistance even if eliminating a barrier metal layer that normally is disposed between a Cu alloy wiring film and a semiconductor layer, and wiring structure with excellent adhesion. The wiring structure is provided with a semiconductor layer, and a Cu alloy layer, on a substrate in this order from the substrate side. A laminated structure is included between the semiconductor layer, and the Cu alloy layer. The laminated structure is composed of a (N, C, F, O) layer which contains at least one element selected from among a group composed of nitrogen, carbon, fluorine, and oxygen, and a Cu—Si diffusion layer which includes Cu and Si, in this order from the substrate side. At least one element selected from among the group composed of nitrogen, carbon, fluorine, and oxygen that composes the (N, C, F, O) layer is bonded to Si in the semiconductor layer. The Cu alloy layer is a laminated structure containing a Cu—X alloy layer (a first layer) and a second layer.

摘要翻译： 公开了即使消除通常设置在Cu合金布线膜和半导体层之间的阻挡金属层以及具有优异的粘附性的布线结构，也可以获得优异的低接触电阻的布线结构。 布线结构在基板上依次从基板侧设置有半导体层和Cu合金层。 在半导体层和Cu合金层之间包含层叠结构。 层叠结构由含有选自氮，碳，氟和氧中的至少一种元素的（N，C，F，O）层构成，Cu-Si扩散层包含Cu和 Si，从衬底侧依次。 构成（N，C，F，O）层的由氮，碳，氟和氧构成的组中的至少一种元素与半导体层中的Si键合。 Cu合金层是含有Cu-X合金层（第一层）和第二层的层叠结构。

公开(公告)号：US08252681B2

公开(公告)日：2012-08-28

申请号：US12536865

申请日：2009-08-06

申请人： Jeong-Do Ryu ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Dong-Chan Kim ,  Jong-Ryeol Yoo ,  Seong-Hoon Jeong ,  Jong-Hoon Kang

发明人： Jeong-Do Ryu ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Dong-Chan Kim ,  Jong-Ryeol Yoo ,  Seong-Hoon Jeong ,  Jong-Hoon Kang

IPC分类号： H01L21/44

CPC分类号： H01L21/28061 ,  H01L21/28247 ,  H01L21/3211 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1104

摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

摘要翻译： 形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。 使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。 可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。 然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。 在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。