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公开(公告)号：US20250061065A1
公开(公告)日：2025-02-20
申请号：US18781989
申请日：2024-07-23
Applicant: Micron Technology, Inc.
Inventor： Melky Arputharaja Siluvainathan
Abstract: A first set of parameter values are programed to a first set of sequencer registers. A second set of parameter values are programmed to a second set of sequencer registers. In response to a detecting a triggering event, a hardware sequencer performs the following operations: transfer the first set of parameter values from the first set of sequencer registers to a first set of link training registers, transfer the second set of parameter values from the second set of sequencer registers to a second set of link training registers, and initiate one end of a communication link training with a host.
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公开(公告)号：US20250061058A1
公开(公告)日：2025-02-20
申请号：US18778600
申请日：2024-07-19
Applicant: Micron Technology, Inc.
Abstract: Apparatuses, systems, and methods for block status parity data are described. An example method includes storing block status data associated with at least one block of a non-volatile memory that indicates a status of the at least one block of memory within a controller. The example method further comprises storing parity data that corresponds to the block status data. The example method further comprises prior to writing the block status data to the non-volatile memory, comparing the stored block status data to the parity data.
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83.发明申请公开(公告)号：US20250061056A1
公开(公告)日：2025-02-20
申请号：US18790537
申请日：2024-07-31
Applicant: Micron Technology, Inc.
Inventor： Sujeet Ayyapureddi
IPC: G06F12/02
Abstract: A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.
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公开(公告)号：US20250061021A1
公开(公告)日：2025-02-20
申请号：US18814142
申请日：2024-08-23
Applicant: Micron Technology, Inc.
Inventor： Crescenzo Attanasio , Carminantonio Manganelli , Massimo Iaculo , Paolo Papa , Antonio Eliso
Abstract: Methods, systems, and devices for device fault condition reporting are described. A host system may transmit, to a memory system, a command to perform an operation. The memory system may receive the command and identify a fault condition associated with performing the operation. The memory system may transmit, to the host system, a message that indicates the fault condition. After the memory system transmits the message, the memory system may enter a safe mode of operation based on identifying the fault condition.
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公开(公告)号：US20250061016A1
公开(公告)日：2025-02-20
申请号：US18784572
申请日：2024-07-25
Applicant: Micron Technology, Inc.
IPC: G06F11/10
Abstract: Apparatuses, systems, and methods for block status data reset are described. An example method includes sending a command, from a controller, to access at least one block of a first memory device. The example method further comprises receiving a failure message from the first memory device due to the at least one block being tagged as a bad block in block status data of the first memory device. The example method further comprises in response to receiving the failure message, resetting the block status data by reloading previously stored block status data from a second memory device.
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Patent Agency Ranking
公开(公告)号：US20250060902A1
公开(公告)日：2025-02-20
申请号：US18938813
申请日：2024-11-06
Applicant: Micron Technology, Inc.
Inventor： Reshmi Basu
Abstract: Systems, apparatuses, and methods related to object management in tiered memory systems are discussed. An example method can include determining a type of characteristic set for each of a plurality of memory objects to be written to a memory system. The memory system can include a first memory device and a second memory device. The method can further include configuring each of the plurality of memory objects to be written to the memory system in the first memory device or the second memory device based on the determination of the type of characteristic set associated with each of the plurality of memory objects. The method can further include writing each of the plurality of memory objects to the first memory device or the second memory device based on the configuration of each of the plurality of memory objects.
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公开(公告)号：US20250060875A1
公开(公告)日：2025-02-20
申请号：US18933971
申请日：2024-10-31
Applicant: Micron Technology, Inc.
Inventor： Sriteja Yamparala , Tawalin Opastrakoon
IPC: G06F3/06
Abstract: A method can include identifying one or more candidate memory blocks that are available for garbage collection, determining a respective erase depth level for each candidate memory block based on one or more block characteristics of the candidate memory block, erasing the candidate memory blocks, wherein each of the candidate memory blocks is erased in accordance with the respective erase depth level determined for the candidate memory block, receiving a request to write data subsequent to erasing the candidate memory blocks, and, responsive to receiving the request to write data, selecting a first memory block from the erased candidate memory blocks in accordance with the respective erase depth level of each of the erased candidate memory blocks. The block characteristics of the candidate memory block can include a program erase count and/or a temperature of the candidate memory block.
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公开(公告)号：US12232432B2
公开(公告)日：2025-02-18
申请号：US18617007
申请日：2024-03-26
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Enrico Varesi , Paolo Fantini
Abstract: Methods, systems, and devices for techniques for memory cells with sidewall and bulk regions in vertical structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. The bulk region may extend between the first electrode and the sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. Also, the sidewall region may separate the bulk region from the second electrode.
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89.发明授权公开(公告)号：US12230608B2
公开(公告)日：2025-02-18
申请号：US17478284
申请日：2021-09-17
Applicant: Micron Technology, Inc.
Inventor： Travis M. Jensen , Raj K. Bansal
IPC: H01L25/065 , H01L21/56 , H01L23/00 , H01L25/00
Abstract: A semiconductor device has first and second dies forming a die stack. Molding material encapsulates the die stack and forms an upper molded surface of the die stack. First conductive traces are coupled to the first die and extend from between the first and second die to corresponding first via locations in the molding material beyond a first side edge of the die stack. Second conductive traces coupled to an active surface of the second die opposite the first die extend to corresponding second via locations. Each first via location is vertically aligned with one of the second via locations. Through mold vias extend through the molding material between vertically aligned via locations to contact with corresponding conductive traces of the first and second dies, while the molding material that extends between the first conductive traces and the upper molded surface is free from any TMV.
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公开(公告)号：US12230332B2
公开(公告)日：2025-02-18
申请号：US17931935
申请日：2022-09-14
Applicant: Micron Technology, Inc.
Inventor： Shakeel Isamohiuddin Bukhari , Mark Ish
Abstract: Implementations described herein relate to suspending memory erase operations to perform high priority memory commands. In some implementations, a memory device may detect, while an active stage of an erase operation is being performed by the memory device, a pending memory command with a higher priority than the erase operation. The memory device may selectively suspend the active stage of the erase operation, to allow the pending memory command to be executed, based on the active stage of the erase operation that is being performed and/or a value of a suspend determination timer associated with suspending the active stage of the erase operation.
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