公开(公告)号：US20220391127A1

公开(公告)日：2022-12-08

申请号：US17339660

申请日：2021-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tawalin Opastrakoon ,  Renato C. Padilla ,  Michael G. Miller ,  Christopher M. Smitchger ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.

公开(公告)号：US11507304B1

公开(公告)日：2022-11-22

申请号：US17339660

申请日：2021-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tawalin Opastrakoon ,  Renato C. Padilla ,  Michael G. Miller ,  Christopher M. Smitchger ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Vamsi Pavan Rayaprolu

IPC: G06F12/00 ,  G06F3/06

Abstract: A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.

公开(公告)号：US20220310190A1

公开(公告)日：2022-09-29

申请号：US17212531

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/50 ,  G11C29/00 ,  G11C16/10 ,  G11C16/26

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.

公开(公告)号：US20220188226A1

公开(公告)日：2022-06-16

申请号：US17123244

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G06F12/06 ,  G06F1/28

Abstract: An amount of threshold voltage distribution shift is determined. The threshold voltage distribution shift corresponds to an amount of time after programming of a reference page of a block of a memory device. A program-verify voltage is adjusted based on the amount of threshold voltage distribution shift to obtain an adjusted program-verify voltage. Using the adjusted program-verify voltage, a temporally subsequent page of the block is programmed at a time corresponding to the amount of time after the programming of the reference page.

公开(公告)号：US12086427B2

公开(公告)日：2024-09-10

申请号：US17677641

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F1/28 ,  G06F1/08 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F1/08 ,  G06F1/28 ,  G06F3/0653 ,  G06F3/0673

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

公开(公告)号：US11715541B2

公开(公告)日：2023-08-01

申请号：US17867538

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Renato C. Padilla ,  Sampath K. Ratnam ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Gary F. Besinga ,  Michael G. Miller ,  Tawalin Opastrakoon

IPC: G11C29/10 ,  G06F11/07 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C29/10 ,  G06F11/076 ,  G06F11/0736 ,  G06F11/0757 ,  G06F11/1048 ,  G11C29/52

Abstract: A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.

公开(公告)号：US11456051B1

公开(公告)日：2022-09-27

申请号：US17212531

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G11C29/44 ,  G11C29/42 ,  G11C16/26 ,  G11C29/00 ,  G11C16/10 ,  G11C29/50

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.

公开(公告)号：US20220199179A1

公开(公告)日：2022-06-23

申请号：US17127012

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Renato C. Padilla ,  Sampath K. Ratnam ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Gary F. Besinga ,  Michael G. Miller ,  Tawalin Opastrakoon

IPC: G11C29/10

Abstract: In one embodiment, a system maintains metadata associating each block of a plurality of blocks of the memory device with a corresponding frequency access group, where each frequency access group is associated with a corresponding scan frequency. The system determines that a first predetermined time period has elapsed since a last scan operation performed with respect to one or more blocks of the memory device, where the first predetermined time period specifies a first scan frequency. The system selects, based on the metadata, at least one block from a first frequency access group associated with the first scan frequency. The system performs a scan operation with respect to the selected block.

公开(公告)号：US20250060875A1

公开(公告)日：2025-02-20

申请号：US18933971

申请日：2024-10-31

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Tawalin Opastrakoon

IPC: G06F3/06

Abstract: A method can include identifying one or more candidate memory blocks that are available for garbage collection, determining a respective erase depth level for each candidate memory block based on one or more block characteristics of the candidate memory block, erasing the candidate memory blocks, wherein each of the candidate memory blocks is erased in accordance with the respective erase depth level determined for the candidate memory block, receiving a request to write data subsequent to erasing the candidate memory blocks, and, responsive to receiving the request to write data, selecting a first memory block from the erased candidate memory blocks in accordance with the respective erase depth level of each of the erased candidate memory blocks. The block characteristics of the candidate memory block can include a program erase count and/or a temperature of the candidate memory block.

公开(公告)号：US20240427507A1

公开(公告)日：2024-12-26

申请号：US18827515

申请日：2024-09-06

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F3/06 ,  G06F1/08 ,  G06F1/28

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.