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129 条记录 (耗时 0.028 秒)

    Efficient pitch multiplication process
    81.
    发明授权
    Efficient pitch multiplication process 有权
    高效的音调乘法过程

    公开(公告)号：US08012674B2

    公开(公告)日：2011-09-06

    申请号：US12687005

    申请日：2010-01-13

    申请人： Mark Fischer ,  Stephen Russell ,  H. Montgomery Manning

    发明人： Mark Fischer ,  Stephen Russell ,  H. Montgomery Manning

    IPC分类号： G03F7/26

    CPC分类号： H01L29/06 ,  H01L21/0338 ,  H01L21/3088

    摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.

    摘要翻译： 通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。 通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。 将图案转移到无定形碳层。 侧壁间隔物形成在图案化无定形碳层的侧壁上。 沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。 除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。 去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。 将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

    MULTI-DIMENSIONAL CONTENT ORGANIZATION AND DELIVERY
    82.
    发明申请
    MULTI-DIMENSIONAL CONTENT ORGANIZATION AND DELIVERY 审中-公开
    多维内容组织和交付

    公开(公告)号：US20110106808A1

    公开(公告)日：2011-05-05

    申请号：US12857364

    申请日：2010-08-16

    申请人： Alexandre Hersans ,  Mark Fischer ,  Orjan Kjellberg ,  Oliver Pin ,  Sonali Agrawal ,  Walter Macklem

    发明人： Alexandre Hersans ,  Mark Fischer ,  Orjan Kjellberg ,  Oliver Pin ,  Sonali Agrawal ,  Walter Macklem

    IPC分类号： G06F17/30

    CPC分类号： G06F16/2264 ,  G06F16/283 ,  G06F16/90328

    摘要： The present disclosure provides novel systems and methods for providing multi-dimensional categorization within a multi-tenant database system (“MTS”). Data items in entities stored in a MTS may be categorized along one or more category dimensions. A search query may include one or more selected categories in one or more category dimensions. Categorization methodologies include multi-selection, multi-position, and combinations thereof. Users of the MTS may also be categorized along one or more category dimensions. A filter may present a subset of data items relevant to a user in accordance with their categorization.

    摘要翻译： 本公开提供了用于在多租户数据库系统（“MTS”）内提供多维分类的新型系统和方法。 存储在MTS中的实体中的数据项可以沿着一个或多个类别维分类。 搜索查询可以包括一个或多个类别维度中的一个或多个所选择的类别。 分类方法包括多选择，多位置及其组合。 MTS的用户也可以按照一个或多个类别维度进行分类。 过滤器可以根据其分类呈现与用户相关的数据项的子集。

    SEMICONDUCTOR PROCESSING METHODS
    83.
    发明申请
    SEMICONDUCTOR PROCESSING METHODS 有权
    半导体处理方法

    公开(公告)号：US20100304560A1

    公开(公告)日：2010-12-02

    申请号：US12855585

    申请日：2010-08-12

    申请人： Mark Fischer ,  Terrence B. McDaniel

    发明人： Mark Fischer ,  Terrence B. McDaniel

    IPC分类号： H01L21/768

    CPC分类号： H01L23/5225 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material can have electrically isolated segments that are utilized as electrical jumpers for connecting circuit elements. The invention also includes semiconductor constructions comprising the electrically conductive material between line constructions associated with one or both of the pitch region and the peripheral region.

    摘要翻译： 本发明包括在与半导体衬底的外围区域或间距区域相关联的线路构造之间形成导电材料的方法。 导电材料可以结合到电接地屏蔽中，和/或可以被配置成产生磁场偏置。 此外，导电材料可以具有用作连接电路元件的电跳线的电隔离段。 本发明还包括在与线圈结构相关联的线路结构之间包括导电材料的半导体结构，其与音调区域和外围区域中的一个或两个相关联。

    Efficient pitch multiplication process
    85.
    发明授权
    Efficient pitch multiplication process 有权
    高效的音调乘法过程

    公开(公告)号：US07666578B2

    公开(公告)日：2010-02-23

    申请号：US11521851

    申请日：2006-09-14

    申请人： Mark Fischer ,  Stephen Russell ,  H. Montgomery Manning

    发明人： Mark Fischer ,  Stephen Russell ,  H. Montgomery Manning

    IPC分类号： G03F7/26 ,  G03F7/00

    CPC分类号： H01L29/06 ,  H01L21/0338 ,  H01L21/3088

    摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.

    摘要翻译： 通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。 通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。 将图案转移到无定形碳层。 侧壁间隔物形成在图案化无定形碳层的侧壁上。 沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。 除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。 去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。 将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

    Semiconductor Constructions, and DRAM Arrays
    86.
    发明申请
    Semiconductor Constructions, and DRAM Arrays 有权
    半导体结构和DRAM阵列

    公开(公告)号：US20090194802A1

    公开(公告)日：2009-08-06

    申请号：US12186726

    申请日：2008-08-06

    申请人： Mark Fischer

    发明人： Mark Fischer

    IPC分类号： H01L27/108

    CPC分类号： H01L27/108 ,  H01L27/0207 ,  H01L27/10873

    摘要： The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions.

    摘要翻译： 本发明包括与鳍式场效应晶体管（finFET）技术结合使用部分绝缘体上硅（SOI）技术的方法，以形成特别适用于动态随机存取存储器（DRAM）阵列的晶体管。 本发明还包括具有低刷新率的DRAM阵列。 另外，本发明包括含有水平相对的源极/漏极区域和在源极/漏极区域之间的沟道区域的晶体管的半导体构造。 晶体管可以包括围绕通道区域的至少部分的至少四分之三的栅极，并且在一些方面可包括围绕通道区域的至少部分的整体的栅极。

    Method of forming gate arrays on a partial SOI substrate
    87.
    发明授权
    Method of forming gate arrays on a partial SOI substrate 有权
    在部分SOI衬底上形成栅极阵列的方法

    公开(公告)号：US07422960B2

    公开(公告)日：2008-09-09

    申请号：US11436726

    申请日：2006-05-17

    申请人： Mark Fischer

    发明人： Mark Fischer

    IPC分类号： H01L21/8238 ,  H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/76

    CPC分类号： H01L27/108 ,  H01L27/0207 ,  H01L27/10873

    摘要： The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions.

    摘要翻译： 本发明包括与鳍式场效应晶体管（finFET）技术结合使用部分绝缘体上硅（SOI）技术的方法，以形成特别适用于动态随机存取存储器（DRAM）阵列的晶体管。 本发明还包括具有低刷新率的DRAM阵列。 另外，本发明包括含有水平相对的源极/漏极区域和在源极/漏极区域之间的沟道区域的晶体管的半导体构造。 晶体管可以包括围绕通道区域的至少部分的至少四分之三的栅极，并且在一些方面可包括围绕通道区域的至少部分的整体的栅极。

    Fin field emission transistor apparatus and processes
    88.
    发明申请
    Fin field emission transistor apparatus and processes 有权
    鳍场发射晶体管装置和工艺

    公开(公告)号：US20080102570A1

    公开(公告)日：2008-05-01

    申请号：US11591627

    申请日：2006-11-01

    申请人： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

    发明人： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

    IPC分类号： H01L21/84 ,  H01L21/336 ,  H01L29/76

    CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7853 ,  Y10S438/947

    摘要： A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch can be carried out to expose at least a portion of the sidewall, causing the dielectric hard mask to recede to a greater degree in the lateral direction than the vertical direction. The process may include second etching the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded hard mask. The thinned semiconductor fin may have a characteristic dimension that can exceed photolithography limits. Electronic devices may include the thinned semiconductor fin as part of a field effect transistor.

    摘要翻译： 工艺可以包括首先通过与散热片半导体的侧壁邻接的电介质硬掩模蚀刻沟槽隔离电介质。 可以执行第一蚀刻以暴露侧壁的至少一部分，使得电介质硬掩模在横向方向上比垂直方向更大程度地退回。 该方法可以包括第二蚀刻鳍式半导体以实现减薄的半导体鳍片，其已经在横向后退的硬掩模的阴影之下后退。 减薄的半导体鳍片可以具有可超过光刻极限的特征尺寸。 电子器件可以包括作为场效应晶体管的一部分的变薄的半导体鳍片。