公开(公告)号：US20080079357A1

公开(公告)日：2008-04-03

申请号：US11861760

申请日：2007-09-26

申请人： Ryuji ISHII ,  Masaki ITO

发明人： Ryuji ISHII ,  Masaki ITO

IPC分类号： H01L51/54 ,  H01L51/56

CPC分类号： H01L51/5096

摘要： An organic electroluminescence device includes a pair of electrodes; a hole injection layer and a luminescent layer disposed between the pair of electrodes; and a mixing-preventing layer disposed between the hole injection layer and the luminescent layer and preventing mixing of the material constituting the hole injection layer and the material constituting the luminescent layer.

摘要翻译： 有机电致发光器件包括一对电极; 空穴注入层和布置在所述一对电极之间的发光层; 以及设置在空穴注入层和发光层之间的防混合层，防止构成空穴注入层的材料与构成发光层的材料的混合。

公开(公告)号：US20070283358A1

公开(公告)日：2007-12-06

申请号：US11656531

申请日：2007-01-23

申请人： Hironori Kasahara ,  Keiji Kimura ,  Jun Shirako ,  Yasutaka Wada ,  Masaki Ito ,  Hiroaki Shikano

发明人： Hironori Kasahara ,  Keiji Kimura ,  Jun Shirako ,  Yasutaka Wada ,  Masaki Ito ,  Hiroaki Shikano

IPC分类号： G06F9/50

CPC分类号： G06F9/5044 ,  G06F2209/5012 ,  Y02D10/22

摘要： A heterogeneous multiprocessor system including a plurality of processor elements having mutually different instruction sets and structures avoids a specific processor element from being short of resources to improve throughput. An executable task is extracted based on a preset depending relationship between a plurality of tasks, and the plurality of first processors are allocated to a general-purpose processor group based on a depending relationship among the extracted tasks. A second processor is allocated to an accelerator group, a task to be allocated is determined from the extracted tasks based on a priority value for each of tasks, and an execution cost of executing the determined task by the first processor is compared with an execution cost of executing the task by the second processor. The task is allocated to one of the general-purpose processor group and the accelerator group that is judged to be lower as a result of the cost comparison.

摘要翻译： 包括具有相互不同的指令集和结构的多个处理器元件的异构多处理器系统避免了特定的处理器元件缺少资源以提高吞吐量。 基于多个任务之间的预设依赖关系来提取可执行任务，并且基于提取的任务之间的依赖关系将多个第一处理器分配给通用处理器组。 将第二处理器分配给加速器组，基于每个任务的优先级值从所提取的任务确定要分配的任务，并且将由第一处理器执行所确定的任务的执行成本与执行成本进行比较 由第二处理器执行任务。 该任务被分配给作为成本比较的结果被判断为较低的通用处理器组和加速器组中的一个。

公开(公告)号：US20070255929A1

公开(公告)日：2007-11-01

申请号：US11660104

申请日：2006-04-12

申请人： Hironori Kasahara ,  Keiji Kimura ,  Jun Shirako ,  Masaki Ito ,  Hiroaki Shikano

发明人： Hironori Kasahara ,  Keiji Kimura ,  Jun Shirako ,  Masaki Ito ,  Hiroaki Shikano

IPC分类号： G06F9/00

CPC分类号： G06F9/5044 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  G06F8/456 ,  G06F9/30083 ,  G06F9/4893 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22 ,  Y02D10/24

摘要： Provided is a multiprocessor system and a compiler used in the system for automatically extracting tasks having parallelism from an input program to be processed, performing scheduling to efficiently operate processor units by arranging the tasks according to characteristics of the processor units, and generating codes for optimizing a system frequency and a power supply voltage by estimating a processing amount of the processor units.

摘要翻译： 提供了一种在系统中使用的多处理器系统和编译器，用于从要处理的输入程序自动提取具有并行性的任务，通过根据处理器单元的特性布置任务来执行调度以有效地操作处理器单元，并且生成用于优化的代码 通过估计处理器单元的处理量来确定系统频率和电源电压。

公开(公告)号：US20070117386A1

公开(公告)日：2007-05-24

申请号：US11598537

申请日：2006-11-13

申请人： Takenori Narita ,  Masaki Ito ,  Kenji Sameshima

发明人： Takenori Narita ,  Masaki Ito ,  Kenji Sameshima

IPC分类号： H01L21/44 ,  H01L21/461 ,  H01L23/48

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

摘要： The CMP technology is provided of providing a damascene wiring structure having a plural-layer wiring that is excellent in flatness and removability of Cu residue. An evaluation substrate is provided for evaluating a condition of a CMP that is employed for configuring a semiconductor device having a plurality of wirings in a vertical direction, and the evaluation substrate comprises: a substrate; a first groove formed on the substrate; a second groove formed on the substrate; and a material of the wiring provided in the first groove and the second groove, wherein a depth of the second groove is shallower than that of the first groove.

摘要翻译： 提供CMP技术提供一种具有优异的Cu残余物的平整度和可移除性的多层布线的镶嵌布线结构。 提供了一种用于评估用于构造具有在垂直方向上具有多个布线的半导体器件的CMP的条件的评估基板，并且所述评估基板包括：基板; 形成在所述基板上的第一槽; 形成在所述基板上的第二槽; 以及设置在第一槽和第二槽中的配线的材料，其中第二槽的深度比第一槽的深度浅。

公开(公告)号：US20060143035A1

公开(公告)日：2006-06-29

申请号：US11072271

申请日：2005-03-07

申请人： Masaki Ito

发明人： Masaki Ito

IPC分类号： G06Q99/00

CPC分类号： G06F15/7867 ,  G06Q30/0283

摘要： Since a semiconductor-integrated device or software that runs on the device is conventionally of a business model to sell it as a component, such device or software does not earn stable profits. In addition, a dynamic reconfigurable processor which dynamically reconfigures a functional cell is capable of realizing a high function, which in turn compels a user to pay an added-value that is not used. To solve the problem, with the present invention, in a semiconductor-integrated device incorporating a reconfigurable circuit and a reconfigurable circuit controller which controls the reconfigurable circuit, the reconfigurable circuit controller executes accounting according to reconfiguration status of the functional cell of the reconfigurable circuit and delivers the accounting information to an external accounting controller.

摘要翻译： 由于在设备上运行的半导体集成设备或软件通常是将其作为组件出售的商业模式，因此这种设备或软件不能获得稳定的利润。 此外，动态重构功能单元的动态可重构处理器能够实现高功能，这又强制用户支付未使用的附加值。 为了解决这个问题，本发明在可再配置电路的可重构电路和可重构电路控制器的半导体集成装置中，可重构电路控制器根据可重构电路的功能单元的重新配置状态执行计费， 将会计信息提供给外部会计控制器。

公开(公告)号：US07009410B2

公开(公告)日：2006-03-07

申请号：US10279008

申请日：2002-10-24

申请人： Masaki Ito ,  Hideo Onodera ,  Shigeru Iwamoto

发明人： Masaki Ito ,  Hideo Onodera ,  Shigeru Iwamoto

IPC分类号： G01R27/26

CPC分类号： G06K9/00053 ,  G06K9/0002

摘要： Capacitance sensor electrodes are arranged in a form of matrix on a semiconductor substrate and coated with a cover film. These capacitance sensor electrodes are connected to a drive circuit. ESD electrodes are arranged in the vicinities of corner portions of the capacitance sensor electrodes. Each ESD electrode is composed of a film containing, for example, aluminum excellent in conductivity and a TiN film formed thereon. The ESD electrodes are grounded through the semiconductor substrate. On each ESD electrode, a plurality of fine ESD holes reaching the ESD electrode from a surface of the cover film are formed.

公开(公告)号：US20050194085A1

公开(公告)日：2005-09-08

申请号：US11069016

申请日：2005-02-28

申请人： Takayoshi Oga ,  Masao Konishi ,  Masaki Ito

发明人： Takayoshi Oga ,  Masao Konishi ,  Masaki Ito

IPC分类号： B32B18/00 ,  C03B29/00 ,  C04B35/10 ,  C04B35/634 ,  C04B35/638 ,  H01L21/48 ,  H01L23/498 ,  H05K1/03 ,  H05K3/46

CPC分类号： H05K3/4611 ,  B32B18/00 ,  C04B35/632 ,  C04B35/63424 ,  C04B35/638 ,  C04B2235/6567 ,  C04B2237/32 ,  C04B2237/343 ,  C04B2237/525 ,  C04B2237/56 ,  C04B2237/62 ,  C04B2237/66 ,  C04B2237/68 ,  C04B2237/704 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/49883 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/4629 ,  H01L2924/00

摘要： The present invention includes a first lamination step of laminating a green sheet on both sides of an alumina substrate sintered at a temperature higher than the sintering temperature of the green sheet to obtain a laminate; a second lamination step of laminating a green sheet for restraint that does not sinter at the sintering temperature of the green sheet on an outermost layer of the laminate to obtain a second laminate; a binder removal step of heating the second laminate at a first heating temperature in a range from 280° C. to 350° C. for a predetermined time to remove a binder component contained in the green sheet; a burning step of sintering the second laminate at a temperature in a range from 800° C. to 1000° C.; and a restraint layer removal step of removing the green sheet for restraint from the second laminate. By thus optimizing binder removal conditions, in a laminate of a burned alumina substrate and an unburned green sheet, the occurrence of delamination (layer separation) between the burned alumina substrate and the laminated ceramic green sheet is prevented even if materials having different coefficients of thermal expansion are stacked.

摘要翻译： 本发明包括在高于生片的烧结温度的温度下烧结的氧化铝衬底的两侧层压生片的第一层压步骤，以获得层压体; 第二层压步骤，在所述层压板的最外层上层压不会在所述生片的烧结温度下烧结的用于约束的生片，以获得第二层压体; 粘合剂去除步骤，在280℃至350℃的第一加热温度下加热所述第二层压体一段预定时间以除去所述生片中所含的粘合剂组分; 在800℃至1000℃的温度下烧结第二层压体的燃烧步骤; 以及约束层去除步骤，用于从所述第二层压体去除所述生片以限制。 通过如此优化粘合剂去除条件，在烧结的氧化铝基板和未烧结的生片的层叠体中，即使具有不同的热系数的材料也能够防止烧结的氧化铝基板和层叠的陶瓷生片之间发生分层（层分离） 膨胀堆积。

公开(公告)号：US06601972B2

公开(公告)日：2003-08-05

申请号：US10043304

申请日：2002-01-14

申请人： Yujiro Sei ,  Masaki Ito

发明人： Yujiro Sei ,  Masaki Ito

IPC分类号： F21V29/00 ,  F21L14/00 ,  F21L14/02 ,  F21V13/00 ,  F21Y101/00 ,  G01J1/08 ,  G01J3/10 ,  F21V1/00 ,  F21V11/00

CPC分类号： F21L14/023 ,  F21L14/00 ,  G01J1/08 ,  G01J3/10

摘要： In a deuterium lamp box in accordance with the present invention, a wavelength of light different from that of a deuterium lamp can be forwardly let out from a light exit opening. Namely, when the deuterium lamp of a see-through type is lit, the light generated from the deuterium lamp can be let out from the light exit opening. When a second lamp is lit while the deuterium lamp is turned off, the light generated from the second lamp 85 passes through the deuterium lamp while in a state collected by a lens, and is let out from the light exit opening. When the deuterium lamp and the second lamp are lit at the same time, different wavelengths of light are let out from the light exit opening while in a mixed state. Thus, three kinds of light can be made depending on how the lamps are lit, whereby this lamp box is considered to have a versatility much higher than that of a lamp box accommodating only one lamp.

公开(公告)号：US06304251B1

公开(公告)日：2001-10-16

申请号：US09345877

申请日：1999-06-30

申请人： Masaki Ito ,  Masato Uehara ,  Hiroki Shoya ,  Tadashi Yanagidate

发明人： Masaki Ito ,  Masato Uehara ,  Hiroki Shoya ,  Tadashi Yanagidate

IPC分类号： G09G500

CPC分类号： G06F3/045

摘要： A coordinate input device is disclosed wherein first lead-out electrode portions formed on a lower substrate and second lead-out electrode portions formed on a film substrate are connected to conductor portions, respectively, of a flat cable and are thereby drawn out to the exterior. Therefore, unlike the prior art which requires that third lead-out electrode portions formed on a film substrate be connected to second lead-out electrode portions formed on a lower substrate with use of an electrically conductive adhesive, it is not necessary to do so. Thus, the connecting operation is easy and the coordinate input device of the present invention is superior in productivity and less expensive.

摘要翻译： 公开了一种坐标输入装置，其中形成在下基板上的第一引出电极部分和形成在膜基板上的第二引出电极部分别连接到扁平电缆的导体部分，并因此被拉出到外部 。 因此，与使用导电性粘合剂将形成在膜基板上的第三引出电极部分连接到形成在下基板上的第二引出电极部分的现有技术不同，不需要这样做。 因此，连接动作容易，本发明的坐标输入装置的生产率优异，成本低廉。

公开(公告)号：US4782438A

公开(公告)日：1988-11-01

申请号：US60072

申请日：1987-06-09

申请人： Masayoshi Mizukado ,  Ken Yamazaki ,  Masaki Ito

发明人： Masayoshi Mizukado ,  Ken Yamazaki ,  Masaki Ito

IPC分类号： G05B19/408 ,  G05B19/00

CPC分类号： G05B19/408 ,  G05B2219/36241 ,  G05B2219/45165

摘要： A program translation calculating section translates a machining program of a turret punch press to a form which a laser beam machine is able to put into practice according to first and second translating program groups. The laser beam machine is drive controlled based on the translated machining program.

摘要翻译： 程序转换计算部分将转塔冲压机的加工程序转换成根据第一和第二翻译程序组激光束机器能够投入使用的形式。 基于翻译的加工程序，激光束机被驱动控制。