TRAINING DATA AUGMENTATION DEVICE AND METHOD FOR 3D POSE ESTIMATION

    公开(公告)号:US20240378749A1

    公开(公告)日:2024-11-14

    申请号:US18656127

    申请日:2024-05-06

    Abstract: A training data augmentation method for three-dimensional (3D) pose estimation includes collecting foot coordinates of each of persons appearing in a two-dimensional image, estimating a ground plane in a three-dimensional space based on the collected foot coordinates, generating three-dimensional pose data by moving or rotating at least one person or moving or rotating the ground plane based on two basis vectors perpendicular to a normal vector of the ground plane, mapping the 3D pose data to two-dimensional pose data based on a focal length of a camera obtained by capturing the two-dimensional image and a principal point of coordinates of the two-dimensional image, and acquiring a pair of the 3D pose data and two-dimensional pose data as training data.

    RANDOM ACCESS MEMORY AND METHOD OF FABRICATING THE SAME

    公开(公告)号:US20240349512A1

    公开(公告)日:2024-10-17

    申请号:US18635072

    申请日:2024-04-15

    CPC classification number: H10B53/30

    Abstract: A memory using ferroelectric metal field-effect transistors includes a drain, a source, and a gate formed on a substrate, a gate contact formed on an upper portion of the gate, and a ferroelectric layer disposed between the gate contact and the gate and configured to surround the gate contact, wherein the gate, the ferroelectric layer, and the gate contact operate as a capacitor having a metal-ferroelectric layer-metal (MFM) structure.

    RANDOM ACCESS MEMORY AND METHOD OF FABRICATING THE SAME

    公开(公告)号:US20240349477A1

    公开(公告)日:2024-10-17

    申请号:US18635211

    申请日:2024-04-15

    CPC classification number: H10B12/00

    Abstract: A random access memory includes a first transistor including a first gate extending in a first direction, a second transistor including a second gate extending in a second direction perpendicular to the first direction and formed on an upper portion of the first transistor, and a storage node configured to connect a first gate of the first transistor to a drain of the second transistor and storing data.

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