公开(公告)号：US08847275B2

公开(公告)日：2014-09-30

申请号：US13796753

申请日：2013-03-12

Applicant: STMicroelectronics S.A.

Inventor： Jean Jimenez ,  Philippe Galy ,  Boris Heitz

IPC: H01L29/417 ,  H01L29/74 ,  H01L31/111 ,  H01L29/72 ,  H01L29/73 ,  H01L23/62 ,  H01L27/02 ,  H01L29/87 ,  H01L29/747

CPC classification number: H01L27/0259 ,  H01L27/0262 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/87

Abstract: The component incorporates, in topological terms, a scalable number of triac structures in a concentric annular arrangement. The component can be used with an electronic device to protect against electrostatic discharges. For example, the components can be used to protect the input/output pad, the first power supply terminal, and the second power supply terminal of an integrated circuit against electrostatic discharges.

Abstract translation: 该组件以拓扑学方式并入具有同步环形布置的可缩放数量的三端双向可控硅结构。 该组件可与电子设备一起使用，以防止静电放电。 例如，这些组件可用于保护集成电路的输入/输出焊盘，第一电源端子和第二电源端子免受静电放电。

公开(公告)号：US20140233671A1

公开(公告)日：2014-08-21

申请号：US14177371

申请日：2014-02-11

Applicant: Institut Polytechnique de Bordeaux ,  STMicroelectronics S.A.

Inventor： DIDIER BELOT ,  Yann Deval ,  Francois Rivet

IPC: H04B1/00

CPC classification number: H04B1/0014 ,  H04B1/406 ,  H04B2001/0491

Abstract: A device for generating a signal, including: a balun; and a circuit capable of summing up, on a first access terminal of the balun, currents representative of signals received on first input terminals of the device, and on a second access terminal of the balun, currents representative of signals received on second input terminals of the device.

Abstract translation: 一种用于产生信号的装置，包括：平衡 - 不平衡转换器; 以及能够在所述平衡 - 不平衡变换器的第一接入终端上总和的电流，代表在所述设备的第一输入端子上接收的信号的电流，以及在所述平衡 - 不平衡变换器的第二接入终端上的总和的电流， 装置。

公开(公告)号：US20140217541A1

公开(公告)日：2014-08-07

申请号：US14247084

申请日：2014-04-07

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Michel Marty ,  François Roy ,  Jens Prima

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/1463 ,  H01L27/14683 ,  H01L27/14687 ,  H01L27/14689

Abstract: A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.

Abstract translation: 一种用于形成背面照明图像传感器的方法，包括以下步骤：a）从前表面形成与衬底相反的导电类型的掺杂多晶硅区域，其垂直于正面延伸， 进入第一层; b）使衬底从其后表面变薄到达多晶硅区域，同时保持第一层的条带; c）在所述薄化衬底的后表面上沉积与所述衬底相反的导电类型的掺杂非晶硅层; 和d）在能够将非晶硅层转变成结晶层的温度下退火。

公开(公告)号：US20140183685A1

公开(公告)日：2014-07-03

申请号：US14144168

申请日：2013-12-30

Applicant: Commissariat à I'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics S.A.

Inventor： François Roy ,  Yvon Cazaux

IPC: H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/14614 ,  H01L27/1463 ,  H01L27/14656

Abstract: An image sensor arranged inside and on top of a semiconductor substrate, having a plurality of pixels, each including: a photosensitive area, a read area, and a storage area extending between the photosensitive area and the read area; at least one first insulated vertical electrode extending in the substrate between the photosensitive area and the storage area; and at least one second insulated vertical electrode extending in the substrate between the storage area and the read area.

Abstract translation: 布置在半导体衬底的内部和顶部的具有多个像素的图像传感器，每个像素包括：感光区域，读取区域和在感光区域和读取区域之间延伸的存储区域; 至少一个第一绝缘垂直电极，其在所述基板中在所述光敏区域和所述存储区域之间延伸; 以及在所述存储区域和所述读取区域之间的所述衬底中延伸的至少一个第二绝缘垂直电极。

公开(公告)号：US20140151768A1

公开(公告)日：2014-06-05

申请号：US13692716

申请日：2012-12-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Ullrich Pfeiffer ,  Hani Sherry ,  Andreia Cathelin

IPC: H01L27/146

CPC classification number: H01L27/14612 ,  G01N21/3581 ,  G01S7/352 ,  G01S13/887 ,  G01V8/005

Abstract: A pixel circuit including: a differential detection circuit having first and second transistors coupled in series between differential output nodes of an antenna, the antenna being configured to be sensitive to terahertz radiation, and wherein: a first main conducting node of the first transistor is coupled to a first of the differential output nodes of the antenna; and a first main conducting node of the second transistor is coupled to a second of said differential output nodes of the antenna, wherein second main conducting nodes of the first and second transistors are formed by a common semiconductor region.

Abstract translation: 一种像素电路，包括：差分检测电路，其具有串联耦合在天线的差分输出节点之间的第一和第二晶体管，所述天线被配置为对太赫兹辐射敏感，并且其中：所述第一晶体管的第一主导电节点被耦合 到天线的差分输出节点中的第一个; 并且所述第二晶体管的第一主导电节点耦合到所述天线的所述差分输出节点中的第二个，其中所述第一和第二晶体管的第二主导体节点由公共半导体区域形成。

公开(公告)号：US20140103972A1

公开(公告)日：2014-04-17

申请号：US14050203

申请日：2013-10-09

Applicant: MentorGraphics Corporation ,  STMicroelectronics S.A.

Inventor： Anna Asquini ,  Vincent Vallet

IPC: H03K3/017

CPC classification number: H03K3/017 ,  G06F1/10 ,  G06F1/12 ,  H03K5/1252

Abstract: A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.

Abstract translation: 一种占空比保护电路，包括适于在输入线路上接收第一时钟信号的第一同步装置，并且响应于第一时钟信号的第一时钟转换而产生第二时钟信号的第一时钟转变; 以及复位电路，其耦合到所述输入线并且适于通过在所述第一时钟信号的所述第一时钟转换之后复位所述第一同步器件时间延迟来产生所述第二时钟信号的第二时钟转变。

公开(公告)号：US20130335666A1

公开(公告)日：2013-12-19

申请号：US13920206

申请日：2013-06-18

Applicant: Commissariat a I'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics S.A.

Inventor： Michel Marty ,  Flavien Hirigoyen ,  Josep Segura Puchades ,  Hélène Wehbe-Alause ,  Umberto Rossini

IPC: G02F1/1368 ,  H01L33/36

CPC classification number: G02F1/1368 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136277 ,  G02F2001/136281 ,  H01L33/36

Abstract: A nanoprojector panel formed of an array of cells, each cell including a liquid crystal layer between upper and lower transparent electrodes, a MOS control transistor being arranged above the upper electrode, each transistor being covered with at least three metallization levels. The transistor of each cell extends in a corner of the cell so that the transistors of an assembly of four adjacent cells are arranged in a central region of the assembly. The upper metallization level extends above the transistors of each the assembly of four adjacent cells. The panel includes, for each assembly of four adjacent cells, a first conductive ring surrounding the transistors, the first ring extending from the lower metallization level to the upper electrode of each cell, with an interposed insulating material.

Abstract translation: 一种由单元阵列形成的纳米光电板面板，每个单元包括上透明电极和下透明电极之间的液晶层，MOS控制晶体管布置在上电极上方，每个晶体管被覆盖有至少三个金属化水平。 每个单元的晶体管延伸在单元的角部，使得四个相邻单元的组件的晶体管被​​布置在组件的中心区域中。 上部金属化水平延伸到四个相邻单元的每个组件的晶体管之上。 对于四个相邻电池的每个组件，面板包括围绕晶体管的第一导电环，第一环从下部金属化层延伸到每个电池的上部电极，并具有插入的绝缘材料。

公开(公告)号：US20130181785A1

公开(公告)日：2013-07-18

申请号：US13745634

申请日：2013-01-18

Applicant: STMicroelectronics S.A. ,  International Business Machines Corporation

Inventor： Yvan Morandini ,  Romain Debrouke

IPC: H03B28/00 ,  H03H11/00

CPC classification number: H03B28/00 ,  H03B5/12 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1253 ,  H03B5/1265 ,  H03H11/00 ,  H03J3/20

Abstract: A variable capacitance device including: first and second transistors coupled in series by their main current nodes between first and second nodes of the device, a control node of the first transistor being adapted to receive a first control signal, and a control node of the second transistor being adapted to receive a second control signal; and control circuitry adapted to generate the first and second control signals from a selection signal.

Abstract translation: 一种可变电容器件，包括：第一和第二晶体管，其由器件的第一和第二节点之间的主要电流节点串联连接，第一晶体管的控制节点适于接收第一控制信号，第二晶体管的控制节点 晶体管适于接收第二控制信号; 以及适于从选择信号产生第一和第二控制信号的控制电路。

公开(公告)号：US20040257008A1

公开(公告)日：2004-12-23

申请号：US10812843

申请日：2004-03-30

Applicant: STMicroelectronics S.A.

Inventor： Jean-Michel Moreau

IPC: G09G001/04

CPC classification number: H04N3/16

Abstract: The invention concerns a scanning circuit, comprising a power supply providing a negative voltage on a first terminal (Tdown), an intermediate voltage on a second terminal (Gnd) and a positive voltage on a terminal of a switch (S), the other terminal of the switch being connected to a third terminal (Tup), a control circuit (6) supplied by connections to the second and third terminals, a differential amplifier receiving a positive and a negative input signal provided by the control circuit, a power amplifier controlled by the differential amplifier, both amplifiers being supplied by connections to the first and third terminals, a deflection coil (Ly) connected between the output of the power amplifier and the second terminal, biasing means setting, when the switch is open, the output of the differential amplifier so that the possible current paths through the power amplifier between the deflection coil and the first terminal are cut.

Abstract translation: 本发明涉及一种扫描电路，包括在第一端子（Tdown）上提供负电压的电源，第二端子上的中间电压（Gnd）和开关（S）的端子上的正电压，另一个端子 所述开关连接到第三端子（Tup），通过连接到所述第二和第三端子提供的控制电路（6），接收由所述控制电路提供的正和负输入信号的差分放大器，控制的功率放大器 通过差分放大器，通过连接到第一和第三端子的两个放大器提供连接在功率放大器的输出端和第二端子之间的偏转线圈（Ly），当开关断开时，偏置装置设定输出 差分放大器，使得穿过偏转线圈和第一端子之间的功率放大器的可能电流路径被切断。

公开(公告)号：US20040252536A1

公开(公告)日：2004-12-16

申请号：US10862057

申请日：2004-06-04

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant

IPC: G11C027/00

CPC classification number: G11C15/04

Abstract: A CAM cell with masking made in the form of an integrated circuit, including a first storage cell including a first transistor, first and second inverters in anti-parallel, and a second transistor; a comparison cell, including third and fourth transistors controlling a fifth transistor, connected in series with a sixth inhibiting transistor to a result line; and a second storage cell, including a seventh transistor in series with two inverters in anti-parallel and an eighth transistor, the second storage cell controlling the inhibiting transistor. The first, second, seventh, and eighth transistors may be N-channel transistors, and the third, fourth, fifth, and sixth transistors may be P-channel transistors.

Abstract translation: 具有以集成电路形式形成的掩蔽的CAM单元，包括：第一存储单元，包括第一晶体管，反并联的第一和第二反相器以及第二晶体管; 比较单元，包括控制第五晶体管的第三和第四晶体管，与第六抑制晶体管串联连接到结果行; 以及第二存储单元，其包括与反并联的两个反相器串联的第七晶体管和第八晶体管，所述第二存储单元控制所述抑制晶体管。 第一，第二，第七和第八晶体管可以是N沟道晶体管，并且第三，第四，第五和第六晶体管可以是P沟道晶体管。