公开(公告)号：US20210124710A1

公开(公告)日：2021-04-29

申请号：US17139621

申请日：2020-12-31

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Leah Shalev ,  Nafea Bshara ,  Guy Nakibly ,  Georgy Machulsky

IPC: G06F15/167 ,  H04L29/06 ,  G06F16/22

Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

公开(公告)号：US10963414B2

公开(公告)日：2021-03-30

申请号：US16287986

申请日：2019-02-27

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F15/78 ,  G06F9/445 ,  G06F13/42

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US20210084128A1

公开(公告)日：2021-03-18

申请号：US17247147

申请日：2020-12-01

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Erez Izenberg ,  Nafea Bshara

IPC: H04L29/06 ,  H04L12/861 ,  H04L12/931 ,  H04L12/721 ,  H04L12/741 ,  H04L12/851 ,  H04L12/801 ,  G06F16/182 ,  G06F16/245 ,  G06F16/00 ,  G06F16/13

Abstract: A packet processing technique can include selecting a protocol field from the packet, and performing a comparison of the selected protocol field with comparison data in a compare logic array to output a protocol index. The protocol index can be used as an address to read parsing commands from a parse control table, and a parse result can be generated based on executing the parsing commands on the packet. The parse results are used to derive a parse result vector, which can be used by a forwarding engine to forward the packet.

公开(公告)号：US10911358B1

公开(公告)日：2021-02-02

申请号：US16384745

申请日：2019-04-15

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Benzi Denkberg ,  Erez Izenberg ,  Nafea Bshara ,  Uri Leder ,  Ofer Frishman

IPC: H04L12/747 ,  G06F12/0802 ,  H04L12/861 ,  H04L12/931 ,  H04L29/06

Abstract: A data or packet processing device such as a network interface controller may include cache control logic that is configured to obtain a set of memory descriptors associated with a queue from the memory. The set of descriptors can be stored in the cache. When a request for processing a data packet associated with the queue is received, the cache control logic can determine that the cache is storing memory descriptors for processing the data packet, and provide the memory descriptors used for processing the packet.

公开(公告)号：US10884974B2

公开(公告)日：2021-01-05

申请号：US16702187

申请日：2019-12-03

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Leah Shalev ,  Nafea Bshara ,  Guy Nakibly ,  Georgy Machulsky

IPC: G06F15/167 ,  H04L29/06 ,  G06F16/22

Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

公开(公告)号：US10742555B1

公开(公告)日：2020-08-11

申请号：US15838245

申请日：2017-12-11

Applicant: Amazon Technologies, Inc.

Inventor： Leah Shalev ,  Ron Diamant ,  Erez Izenberg ,  Nafea Bshara

IPC: H04L12/803 ,  H04L12/26 ,  H04L29/06 ,  H04L12/721 ,  H04L12/743 ,  H04L12/707 ,  H04J3/06

Abstract: A method and corresponding apparatus for detecting network congestion. The method includes capturing, using a local clock of a sender device, a send time of an outgoing packet sent from the sender device to a receiver device through a forward route, and capturing, using the local clock of the sender device, a receive time of an acknowledgment packet sent from the receiver device to the sender device through a backward route. The acknowledgment packet contains timing information, generated using a local clock of the receiver device, for determining an internal latency of the receiver device. A round trip time is computed as a difference between the send time and the receive time. The internal latency is subtracted from the round trip time to compute a total propagation time. If the total propagation time is above a threshold, the forward route and the backward route are changed.

公开(公告)号：US20190213155A1

公开(公告)日：2019-07-11

申请号：US16361007

申请日：2019-03-21

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Erez Izenberg

IPC: G06F13/362 ,  G06F13/40 ,  G06F9/50

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

公开(公告)号：US10282330B2

公开(公告)日：2019-05-07

申请号：US15280624

申请日：2016-09-29

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Erez Izenberg

IPC: G06F15/18 ,  G06F13/362 ,  G06F13/40 ,  G06F9/50

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

公开(公告)号：US10218576B1

公开(公告)日：2019-02-26

申请号：US16110270

申请日：2018-08-23

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Leah Shalev ,  Nafea Bshara ,  Erez Izenberg

IPC: G06F15/16 ,  H04L12/24 ,  H04L29/06 ,  G06F3/06

Abstract: Technologies for performing controlled bandwidth expansion are described. For example, a storage server can receive a request from a client to read compressed data. The storage server can obtain individual storage units of the compressed data. The storage server can also obtain a compressed size and an uncompressed size for each of the storage units. The storage server can generate network packet content comprising the storage units and associated padding such that the size of the padding for a given storage is based on the uncompressed and compressed sizes of the given storage unit. The storage server can send the network packet content to the client in one or more network packets. The client can receive the network packets, discard the padding, and decompress the compressed data from the storage units.

公开(公告)号：US20190020538A1

公开(公告)日：2019-01-17

申请号：US16120134

申请日：2018-08-31

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Nafea Bshara ,  Christopher Pettey ,  Curtis Karl Ohrt

IPC: H04L12/24 ,  G06F9/50 ,  G06F15/78 ,  G06F9/455

Abstract: A resource manager of a virtualized computing service indicates to a client that FPGA-enabled compute instances are supported at the service. From a set of virtualization hosts of the service, a particular host from which an FPGA is accessible is selected for the client based on an indication of computation objectives of the client. Configuration operations are performed to prepare the host for the application, and an FPGA-enabled compute instance is launched at the host for the client.