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公开(公告)号：US20170075857A1
公开(公告)日：2017-03-16
申请号：US15360853
申请日：2016-11-23
Applicant: Amazon Technologies, Inc.
Inventor： Erez Izenberg , Leah Shalev , Georgy Machulsky , Nafea Bshara
IPC: G06F15/173 , G06F3/06 , H04L29/08
CPC classification number: G06F15/17331 , G06F3/0611 , G06F3/0659 , G06F3/067 , H04L67/1097
Abstract: According to an embodiment of the invention there may be provided a method for hybrid remote direct memory access (RDMA), the method may include: (i) receiving, by a first computer, a packet that was sent over a network from a second computer; wherein the packet may include data and metadata; (ii) determining, in response to the metadata, whether the data should be (a) directly written to a first application memory of the first computer by a first hardware accelerator of the first computer; or (b) indirectly written to the first application memory; (iii) indirectly writing the data to the first application memory if it determined that the data should be indirectly written to the first application memory; (iv) if it determined that the data should be directly written to the first application memory then: (iv.a) directly writing, by the first hardware accelerator the data to the first application memory without writing the data to any buffer of the operating system; and (iv.b) informing a first RDMA software module, by the first hardware accelerator, that the data was directly written to the first application memory; and (v) notifying, by the first RDMA software module, a second computer about a completion of an RDMA transaction during which the data was directly written to the first application memory.
Abstract translation: 根据本发明的实施例，可以提供一种用于混合远程直接存储器访问（RDMA）的方法，所述方法可以包括：（i）由第一计算机接收通过网络从第二计算机发送的分组 ; 其中所述分组可以包括数据和元数据; （ii）响应于所述元数据确定所述数据是否应当（a）由所述第一计算机的第一硬件加速器直接写入所述第一计算机的第一应用存储器; 或（b）间接写入第一个应用程序内存; （iii）如果确定数据应间接写入第一应用存储器，则将数据间接写入第一应用存储器; （iv）如果确定数据应直接写入第一应用存储器，则：（iv.a）由第一硬件加速器将数据直接写入第一应用存储器，而不将数据写入任何操作缓冲器 系统; 和（iv.b）通过第一硬件加速器通知第一RDMA软件模块将数据直接写入第一应用存储器; 以及（v）由第一RDMA软件模块通知第二台计算机，其中数据被直接写入到第一应用存储器中，完成RDMA事务。
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公开(公告)号：US09411731B2
公开(公告)日：2016-08-09
申请号：US14829410
申请日：2015-08-18
Applicant: Amazon Technologies, Inc.
Inventor： Adi Habusha , Gil Stoler , Said Bshara , Nafea Bshara
CPC classification number: G06F12/0828 , G06F12/0831 , G06F12/0833 , G06F12/0855 , G06F2212/62 , G06F2212/621 , G11C7/1072
Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.
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公开(公告)号：US12218841B1
公开(公告)日：2025-02-04
申请号：US16712589
申请日：2019-12-12
Applicant: Amazon Technologies, Inc.
Inventor： Leah Shalev , Georgy Zorik Machulsky , Peter Nicholas DeSantis , Nafea Bshara , Omer Ilany
IPC: H04L47/10 , H04L41/0816 , H04L43/0829 , H04L69/16 , H04L69/163
Abstract: Methods and apparatuses for improving network packet transmission performance in terms of latency with reduced packet retransmission times and fewer packet drops in congested networks are provided. Packet-switched networks can experience long delays while waiting for out-of-order packets or re-transmissions of lost packets. In addition, network faults such as transmission path failures can result in excessive delay while attempting to find a new route over which to transmit packets. To improve packet transmission performance, application data may be encapsulated into first network packets by a first transport protocol having an interface exposed to the application, in the first network packets may be encapsulated into second network packets according to a second transport protocol. The second transport protocol can enable the second network packets of a same packet flow to be transmitted across multiple paths over the network.
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公开(公告)号：US20240095367A1
公开(公告)日：2024-03-21
申请号：US17662610
申请日：2022-05-09
Applicant: Amazon Technologies, Inc.
Inventor： Said Bshara , Nafea Bshara , Ali Ghassan Saidi
IPC: G06F21/57
CPC classification number: G06F21/577 , G06F2221/034
Abstract: A data guard circuit can be used to verify encryption of the data traffic on a bus between two integrated circuit (IC) devices. The data guard circuit can monitor the data traffic on the bus to analyze the data traffic based on a configuration. The analysis can be performed by sampling the data traffic, and a statistical data pattern can be identified in the sampled data traffic. The statistical data pattern can be compared with a threshold to determine whether the data traffic is encrypted. The data guard circuit can generate a notification if the data traffic is not encrypted as expected so that an appropriate action can be taken to protect the data.
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公开(公告)号：US11792299B1
公开(公告)日：2023-10-17
申请号：US17806231
申请日：2022-06-09
Applicant: Amazon Technologies, Inc.
Inventor： Said Bshara , Alan Michael Judge , Erez Izenberg , Julien Ridoux , Joshua Benjamin Levinson , Anthony Nicholas Liguori , Nafea Bshara
CPC classification number: H04L67/60 , G06F9/5038 , H04L63/0428 , H04L67/14
Abstract: Various embodiments of apparatuses and methods for multi-cast, multiple unicast, and unicast distribution of messages with time synchronized delivery are described. In some embodiments, the disclosed system and methods include a reference timekeeper providing a reference clock to one or more host computing devices. The one or more host computing devices host compute instances, and also contain respective isolated timing hardware outside the control of the compute instances. The isolated timing hardware of the one or more host computing devices then receive respective packets, and obtain the same time to deliver the respective packets. Each isolated timing hardware provides either the packet, or information to access the packet, to its respective destination compute instance subsequent to determining that the same specified time to deliver the packet has occurred. Thus, the respective packets are delivered near simultaneously to the one or more destination compute instances.
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Patent Agency Ranking
公开(公告)号：US11599821B2
公开(公告)日：2023-03-07
申请号：US16020776
申请日：2018-06-27
Applicant: Amazon Technologies, Inc.
Inventor： Sudipta Sengupta , Poorna Chand Srinivas Perumalla , Dominic Rajeev Divakaruni , Nafea Bshara , Leo Parker Dirac , Bratin Saha , Matthew James Wood , Andrea Olgiati , Swaminathan Sivasubramanian
Abstract: Implementations detailed herein include description of a computer-implemented method. In an implementation, the method at least includes receiving an application instance configuration, an application of the application instance to utilize a portion of an attached accelerator during execution of a machine learning model and the application instance configuration including: an indication of the central processing unit (CPU) capability to be used, an arithmetic precision of the machine learning model to be used, an indication of the accelerator capability to be used, a storage location of the application, and an indication of an amount of random access memory to use.
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公开(公告)号：US11599490B1
公开(公告)日：2023-03-07
申请号：US15913786
申请日：2018-03-06
Applicant: Amazon Technologies, Inc.
Inventor： Georgy Machulsky , Nafea Bshara , Netanel Israel Belgazal , Evgeny Schmeilin , Said Bshara
Abstract: A packet header is received from a host and written to a header queue. A direct memory access (DMA) descriptor is received from the host and written to a packet descriptor queue. The DMA descriptor points to packet data in a host memory. The packet data is fetched from host memory and the packet header and the packet data are provided to a network interface.
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公开(公告)号：US11500719B1
公开(公告)日：2022-11-15
申请号：US16835794
申请日：2020-03-31
Applicant: Amazon Technologies, Inc.
Inventor： Charan Srinivasan , Nafea Bshara
Abstract: To improve the reliability of a memory system, data and error correction codes associated with the data can be stored in a first memory. Parity bits calculated over data bits in the first memory can be stored in a second memory. The parity bits in the second memory can be used to recover errors that are uncorrectable by the error correction codes. The first memory can be implemented, for example, using an emerging memory technology, while the second memory can be implement using a different memory technology.
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公开(公告)号：US11494621B2
公开(公告)日：2022-11-08
申请号：US16020788
申请日：2018-06-27
Applicant: Amazon Technologies, Inc.
Inventor： Sudipta Sengupta , Poorna Chand Srinivas Perumalla , Dominic Rajeev Divakaruni , Nafea Bshara , Leo Parker Dirac , Bratin Saha , Matthew James Wood , Andrea Olgiati , Swaminathan Sivasubramanian
Abstract: Implementations detailed herein include description of a computer-implemented method. In an implementation, the method at least includes receiving an application instance configuration, an application of the application instance to utilize a portion of an attached accelerator during execution of a machine learning model and the application instance configuration including an arithmetic precision of the machine learning model to be used in determining the portion of the accelerator to provision; provisioning the application instance and the portion of the accelerator attached to the application instance, wherein the application instance is implemented using a physical compute instance in a first location, wherein the portion of the accelerator is implemented using a physical accelerator in the second location; loading the machine learning model onto the portion of the accelerator; and performing inference using the loaded machine learning model of the application using the portion of the accelerator on the attached accelerator.
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公开(公告)号：US11474966B2
公开(公告)日：2022-10-18
申请号：US17184507
申请日：2021-02-24
Applicant: Amazon Technologies, Inc.
Inventor： Islam Atta , Christopher Joseph Pettey , Asif Khan , Robert Michael Johnson , Mark Bradley Davis , Erez Izenberg , Nafea Bshara , Kypros Constantinides
Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.
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