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公开(公告)号：US11934070B2
公开(公告)日：2024-03-19
申请号：US17600162
申请日：2020-10-23
Inventor： Quan Gan , Ya Yu , Feng Qu , Yongcan Wang , Fengzhen Lv , Xianjie Shao , Rui Ma
IPC: G02F1/1339 , G02F1/1335
CPC classification number: G02F1/13394 , G02F1/133512 , G02F1/13396
Abstract: Disclosed is a display panel including: first spacer on the array substrate, an orthographic projection of the first spacer on the array substrate being a first pattern extending along a first direction; a second spacer on the counter substrate, an orthographic projection of the second spacer on the array substrate being a second pattern extending along a second direction; at least two third spacers, orthographic projections of which on the array substrate being respectively on two sides of the first pattern along the first direction; at least two fourth spacers, orthographic projections of which on the array substrate being respectively on two sides of the second pattern along the second direction; one of the third spacer and the fourth spacer is on the array substrate, and the other is on the counter substrate.
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公开(公告)号：US11881631B2
公开(公告)日：2024-01-23
申请号：US17621126
申请日：2021-02-26
Inventor： Qianhong Wu , Jingwen Guo , Chunxin Li , Jia Fang , Feng Qu
Abstract: An antenna includes: a substrate; a first reference electrode on a first surface of the substrate; a radiating element on a second surface of the substrate, feeding directions of a first port and a second port of the radiating element are different; and at least one transmission structure on the second surface of the substrate and connected to at least one of the first port and the second port. The transmission structure includes: a signal electrode, a second reference electrode on at least one side of the signal electrode, and at least one membrane bridge; the signal electrode feeds a microwave signal into the radiating element, is positioned in a space surrounded by the membrane bridge and the substrate, and is insulated from the membrane bridge through an interlayer dielectric layer; orthographic projections of the membrane bridge and the second reference electrode on the substrate are overlapped.
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公开(公告)号：US11876274B2
公开(公告)日：2024-01-16
申请号：US17443566
申请日：2021-07-27
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jingwen Guo , Chunxin Li , Qianhong Wu , Yanzhao Li , Feng Qu
Abstract: A phase shifter and an antenna device are provided. The phase shifter includes a substrate, a signal line on the substrate, ground lines in pairs on the substrate, and a capacitance adjusting component. Two ground lines in a same pair of ground lines are on both sides of the signal line and spaced apart from the signal line, respectively. The capacitance adjusting component includes a film bridge, and both ends of the film bridge are on the two ground lines, respectively. The signal line is in a space enclosed by the film bridge and the substrate. The capacitance adjusting component is configured to adjust a capacitance between the film bridge and the signal line to a target capacitance when the capacitance adjusting component receives a bias voltage, and the target capacitance has a linear correlation with a magnitude of the bias voltage.
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公开(公告)号：US11783744B2
公开(公告)日：2023-10-10
申请号：US17445810
申请日：2021-08-24
Inventor： Qiujie Su , Zhihua Sun , Yingmeng Miao , Yinlong Zhang , Feng Qu , Seungmin Lee , Yanping Liao , Xibin Shao
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/0286 , G09G2310/08
Abstract: A gate driving circuit, a method for driving the gate driving circuit, and a display panel. The gate driving circuit includes N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where N, k and K are positive integers, and 1≤k≤K≤N; and an input signal terminal of a n-th stage of shift register is connected to an output signal terminal of a (n−i)-th stage of shift register, and reset signal terminals of the n-th and (n+1)-th stages of shift registers are connected to an output signal terminal of a (n+j)-th stage of shift register, wherein the n is one of an odd number and an even number, where i and j are positive integers, 1
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公开(公告)号：US20230196961A1
公开(公告)日：2023-06-22
申请号：US18082691
申请日：2022-12-16
Inventor： Yingmeng Miao , Changcheng Liu , Zhihua Sun , Yangping Liao , Seungmin Lee , Xibin Shao , Cong Wang , Feng Qu
CPC classification number: G09G3/20 , G11C19/28 , G09G2310/0267 , G09G2300/0408 , G09G2310/08 , G09G2300/08 , G09G2310/0243 , G09G2310/0286
Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n−i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n−i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N−j+1)-th to N-th stages of first shift registers and reset signal terminals of (N−j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.
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Patent Agency Ranking
公开(公告)号：US11636793B2
公开(公告)日：2023-04-25
申请号：US17341756
申请日：2021-06-08
Inventor： Zhihua Sun , Yinlong Zhang , Qiujie Su , Feng Qu , Jing Liu , Yanping Liao , Xibin Shao
IPC: G09G3/20
Abstract: Embodiments of the present disclosure provide a method of driving display, and a display device. The method of driving display includes: scanning, progressively or rows by rows, a plurality of sub-pixels arranged in an N×M array, to turn on each row of sub-pixels scanned, so that a duration in which two adjacent rows of sub-pixels are simultaneously in an ON state is greater than or equal to two times a unit scanning time, wherein the unit scanning time is a time required for scanning a row of sub-pixels, N is an integer greater than 1, and M is an integer greater than 1; and applying data signals to at least two rows of sub-pixels simultaneously in the ON state, so that a duration of applying the data signals to each row of sub-pixels is greater than the unit scanning time.
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公开(公告)号：US11604376B2
公开(公告)日：2023-03-14
申请号：US17412086
申请日：2021-08-25
IPC: G02F1/1333 , G02F1/1335 , G02F1/1345 , G02F1/1362 , G02F1/13357
Abstract: The present disclosure discloses a display apparatus and a manufacturing method of an array substrate comprised therein. The display apparatus includes: a backlight module, a display module located on a light-emitting side of the backlight module, and a shell accommodating the backlight module and the display module. The display module includes: an array substrate and a color film substrate which are opposite to each other, and a first polarizer located on one side, facing away from the color film substrate, of the array substrate. The shell includes: a back part arranged on one side, facing away from the color film substrate, of the backlight module; and a plurality of side parts which are in touch with the back part and perpendicular to the back part.
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公开(公告)号：US20230056588A1
公开(公告)日：2023-02-23
申请号：US17789459
申请日：2021-08-26
Inventor： Jie Yang , Yuansheng Zang , Heng Zhang , Sheng Wang , Hui Wang , Junsheng Chen , Feng Qu , Yan Wang
IPC: G02F1/1362 , G02F1/1333 , G02F1/1335 , G02F1/1339 , G02F1/1368
Abstract: A display device includes a backlight module; a display module located on a light exiting side of the backlight module; and a housing accommodating the backlight module and the display module. The display module includes a display panel including an array substrate and a color film substrate arranged opposite to each other. The color film substrate is located between the array substrate and the backlight module. A first polarizer located on one side of the array substrate away from the color film substrate. A manufacturing method of a display device is also provided.
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公开(公告)号：US20230034489A1
公开(公告)日：2023-02-02
申请号：US17788540
申请日：2021-08-05
Inventor： Jituo TANG , Kun YANG , Zhihua SUN , Feng Qu , Ming DENG , Ruilian LI , Tianxun XIU , Zhun LIN
IPC: G09G3/20
Abstract: The present disclosure relates to a protection circuit for a display device, a display device thereof, and a method for protecting a display device using a protection circuit. The display device includes a gate driving circuit, a level shift circuit, and a power management circuit. The level shift circuit is configured to provide an input signal to a signal input terminal of the gate driving circuit. The power management circuit is configured to provide power to the gate driving circuit. The protection circuit is configured to provide a power control signal to the power management circuit based on a current at the signal input terminal of the gate driving circuit, so that the power management circuit stops providing the power to the gate driving circuit.
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公开(公告)号：US20220101770A1
公开(公告)日：2022-03-31
申请号：US17445810
申请日：2021-08-24
Inventor： Qiujie Su , Zhihua Sun , Yingmeng Miao , Yinlong Zhang , Feng Qu , Seungmin Lee , Yanping Liao , Xibin Shao
Abstract: A gate driving circuit, a method for driving the gate driving circuit, and a display panel. The gate driving circuit includes N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where N, k and K are positive integers, and 1≤k≤K≤N; and an input signal terminal of a n-th stage of shift register is connected to an output signal terminal of a (n−i)-th stage of shift register, and reset signal terminals of the n-th and (n+1)-th stages of shift registers are connected to an output signal terminal of a (n+j)-th stage of shift register, wherein the n is one of an odd number and an even number, where i and j are positive integers, 1
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