公开(公告)号：US06921709B1

公开(公告)日：2005-07-26

申请号：US10620194

申请日：2003-07-15

Applicant: Eric N. Paton ,  Haihong Wang ,  Qi Xiang

Inventor： Eric N. Paton ,  Haihong Wang ,  Qi Xiang

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/84 ,  H01L29/10

CPC classification number: H01L21/84 ,  H01L21/2652 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7842 ,  Y10S438/923 ,  Y10S438/933

Abstract: A method of manufacturing an integrated circuit having a gate structure above a substrate that includes germanium utilizes at least one layer as a seal. The layer advantageously can prevent back sputtering and outdiffusion. A transistor can be formed in the substrate by doping through the layer. Another layer can be provided below the first layer. Layers of silicon dioxide, silicon carbide, silicon nitride, titanium, titanium nitride, titanium/titanium nitride, tantalum nitride, and silicon carbide can be used.

Abstract translation: 制造具有在包括锗的衬底之上的栅极结构的集成电路的方法利用至少一层作为密封。 该层有利地可以防止反溅射和扩散。 可以通过掺杂通过层在衬底中形成晶体管。 可以在第一层下面提供另一层。 可以使用二氧化硅，碳化硅，氮化硅，钛，氮化钛，钛/氮化钛，氮化钽和碳化硅的层。

公开(公告)号：US06852600B1

公开(公告)日：2005-02-08

申请号：US10726472

申请日：2003-12-02

Applicant: Haihong Wang ,  Qi Xiang

Inventor： Haihong Wang ,  Qi Xiang

IPC: H01L21/335 ,  H01L21/336 ,  H01L29/10 ,  H01L29/80 ,  H01L21/76

CPC classification number: H01L29/66431 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/802

Abstract: A strained silicon MOSFET utilizes a strained silicon layer formed on a silicon geranium layer. Strained silicon and silicon germanium are removed at opposing sides of the gate and are replaced by silicon regions. Deep source and drain regions are implanted in the silicon regions, and the depth of the deep source and drain regions does not extend beyond the depth of the silicon regions. By forming the deep source and drain regions in the silicon regions, detrimental effects of the higher dielectric constant and lower band gap of silicon geranium are reduced.

Abstract translation: 应变硅MOSFET利用形成在硅天竺葵层上的应变硅层。 应变硅和硅锗在栅极的相对侧被去除并被硅区域代替。 深源极和漏极区域被注入到硅区域中，并且深源极和漏极区域的深度不延伸超过硅区域的深度。 通过在硅区域形成深源极和漏极区域，降低了硅天竺葵的较高介电常数和较低带隙的有害影响。

公开(公告)号：US06657223B1

公开(公告)日：2003-12-02

申请号：US10282538

申请日：2002-10-29

Applicant: Haihong Wang ,  Qi Xiang

Inventor： Haihong Wang ,  Qi Xiang

IPC: H01L2906

CPC classification number: H01L29/66431 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/802

Abstract: A strained silicon MOSFET utilizes a strained silicon layer formed on a silicon germanium layer. Strained silicon and silicon germanium are removed at opposing sides of the gate and are replaced by silicon regions. Deep source and drain regions are implanted in the silicon regions, and the depth of the deep source and drain regions does not extend beyond the depth of the silicon regions. By forming the deep source and drain regions in the silicon regions, detrimental effects of the higher dielectric constant and lower band gap of silicon germanium are reduced.

Abstract translation: 应变硅MOSFET利用在硅锗层上形成的应变硅层。 应变硅和硅锗在栅极的相对侧被去除并被硅区域代替。 深源极和漏极区域被注入到硅区域中，并且深源极和漏极区域的深度不延伸超过硅区域的深度。 通过在硅区域形成深源极和漏极区域，降低了硅锗的较高介电常数和较低带隙的有害影响。

公开(公告)号：US08554725B2

公开(公告)日：2013-10-08

申请号：US13477999

申请日：2012-05-22

Applicant: Haihong Wang

Inventor： Haihong Wang

IPC: G06F17/30

CPC classification number: G06F17/30174 ,  Y10S707/99952

Abstract: Data replication includes generating replication data that is part of a replicated file system to be sent over a communication channel to a destination replication device; adding additional verification information to at least a portion of the replication data to prevent data corruption; and sending the replication data and the additional verification information over the communication channel to the destination replication device. The replication data with additional verification information is sent over the communication channel using a reliable protocol that allows the replication data to be verified by the reliable protocol at the destination replication device. The reliable protocol is a protocol capable of detecting most but not all data corruption introduced by the communication channel. The additional verification information includes information for verifying that replication data sent using the reliable protocol does not include data corruption that was introduced by the communication channel and undetected by the reliable protocol.

Abstract translation: 数据复制包括生成作为通过通信通道发送到目标复制设备的复制文件系统的一部分的复制数据; 向至少一部分复制数据添加其他验证信息，以防止数据损坏; 以及通过所述通信信道将所述复制数据和所述附加验证信息发送到所述目的地复制设备。 具有附加验证信息的复制数据通过通信通道使用可靠的协议发送，该协议允许复制数据由目的地复制设备上的可靠协议进行验证。 可靠的协议是能够检测通信信道引入的大多数但不是全部数据损坏的协议。 附加验证信息包括用于验证使用可靠协议发送的复制数据不包括由通信信道引入并且不被可靠协议检测到的数据损坏的信息。

公开(公告)号：US07701019B2

公开(公告)日：2010-04-20

申请号：US11356606

申请日：2006-02-17

Applicant: Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

Inventor： Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

IPC: H01L27/088

CPC classification number: H01L29/7843 ,  H01L29/1054 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/933 ,  H01L2924/00

Abstract: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

Abstract translation: 示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。 该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。 沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

公开(公告)号：US20090047770A1

公开(公告)日：2009-02-19

申请号：US12205361

申请日：2008-09-05

Applicant: Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

Inventor： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温过程可以是ALD过程。

公开(公告)号：US06800910B2

公开(公告)日：2004-10-05

申请号：US10335474

申请日：2002-12-31

Applicant: Ming-Ren Lin ,  Jung-Suk Goo ,  Haihong Wang ,  Qi Xiang

Inventor： Ming-Ren Lin ,  Jung-Suk Goo ,  Haihong Wang ,  Qi Xiang

IPC: H01L27105

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

Abstract: A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.

Abstract translation: FinFET器件采用应变硅来增强载流子迁移率。 在一种方法中，FinFET体从覆盖在电介质层上的硅锗层（SiGe）构图。 然后在硅锗FinFET体上形成硅的外延层。 由于本征硅和作为外延硅生长的模板的硅锗晶格的不同维度，在外延硅中引起应变。 与松弛硅相比，应变硅具有增加的载流子迁移率，结果外延应变硅在FinFET中提供增加的载流子迁移率。 因此，可以在采用应变硅沟道层的FinFET中实现更高的驱动电流。

公开(公告)号：US06620671B1

公开(公告)日：2003-09-16

申请号：US09846813

申请日：2001-05-01

Applicant: Haihong Wang ,  Joong Jeon

Inventor： Haihong Wang ,  Joong Jeon

IPC: H01L218238

CPC classification number: H01L21/28194 ,  H01L21/28035 ,  H01L29/4925 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656

Abstract: A method of manufacturing an integrated circuit on a substrate provides a gate structure including single crystalline material. The method can provide a first amorphous or polycrystalline semiconductor layer above a top surface of the substrate and patterning the first amorphous semiconductor layer to form a first gate conductor. The process can also include utilizing solid phase epitaxy to form a single crystal layer above the first gate conductor and patterning the single crystal layer to form a second gate conductor including the single crystal layer.

Abstract translation: 在衬底上制造集成电路的方法提供包括单晶材料的栅极结构。 该方法可以在衬底的顶表面上方提供第一非晶或多晶半导体层，并且对第一非晶半导体层进行构图以形成第一栅极导体。 该方法还可以包括利用固相外延在第一栅极导体上方形成单晶层，并构图单晶层以形成包括单晶层的第二栅极导体。

公开(公告)号：US07713834B2

公开(公告)日：2010-05-11

申请号：US12205361

申请日：2008-09-05

Applicant: Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

Inventor： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温过程可以是ALD过程。

公开(公告)号：US07071065B1

公开(公告)日：2006-07-04

申请号：US10738716

申请日：2003-12-17

Applicant: Qi Xiang ,  Eric N. Paton ,  Haihong Wang

Inventor： Qi Xiang ,  Eric N. Paton ,  Haihong Wang

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66916 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802 ,  Y10S438/933

Abstract: A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed on the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon germanium material. The shallow source and drain extensions do not extend into the strained silicon channel region. By forming the source and drain extensions in silicon germanium material rather than in silicon, source and drain extension distortions caused by the enhanced diffusion rate of boron in silicon are avoided.

Abstract translation: 应变硅p型MOSFET利用形成在硅锗衬底上的应变硅沟道区。 在邻近于应变硅沟道区的端部的硅锗层上形成硅锗区，并且在硅锗材料中注入浅的源极和漏极延伸。 浅源极和漏极延伸部分不延伸到应变硅沟道区域。 通过在硅锗材料而不是在硅中形成源极和漏极延伸，避免了由硅中的增强的扩散速率引起的源极和漏极扩展失真。