公开(公告)号：US20110202897A1

公开(公告)日：2011-08-18

申请号：US13093814

申请日：2011-04-25

申请人： Meng-Kai Hsu ,  Yao-Wen Chang ,  Tung-Chieh Chen

发明人： Meng-Kai Hsu ,  Yao-Wen Chang ,  Tung-Chieh Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A placer produces a global placement plan specifying positions of cell instances and orientations of macros within an integrated circuit (IC) by initially clusterizing cell instances and macros to form a pyramidal hierarchy of blocks. Then the placer iteratively repeats the declusterization and routability improvement process from the highest level to the lowest level of the hierarchy. An objective function is provided in Cartesian coordinate for representing the position of each movable instance and in polar coordinate for representing the orientation of a macro relative to its the center. For each movable instance and each rotatable macro, its position or orientation is determined by conjugate gradient method to minimize total wire length. Finally, the placer uses a look-ahead legalization technique to rotate rotatable macros to legal orientations and move cell instances to legal positions in the end of global placement.

摘要翻译： 放样器通过最初将单元实例和宏聚类以形成块的锥体层次，产生一个全局放置计划，指定集成电路（IC）中宏的位置和宏的位置。 然后，迭代器迭代地重复从层次结构的最高级别到最低级别的分解和路由改进过程。 在笛卡尔坐标中提供了一个目标函数，用于表示每个可移动实例的位置，并以极坐标表示宏相对于其中心的方向。 对于每个可移动实例和每个可旋转宏，其位置或取向由共轭梯度法确定，以使总线长度最小化。 最后，Placer使用先行合法化技术将可旋转的宏转换为法定方向，并在全局放置结束时将单元格实例移动到合法位置。

公开(公告)号：US20110004858A1

公开(公告)日：2011-01-06

申请号：US12550484

申请日：2009-08-31

申请人： Yao-Wen Chang ,  Chin-Hsiung Hsu

发明人： Yao-Wen Chang ,  Chin-Hsiung Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for concurrent migration and decomposition of an integrated circuit layout applicable to double patterning lithography techniques is provided. The method includes cutting a sub-pattern of an initial pattern to configure a potentially conflicting pattern having separate or cutting sections; removing odd cycles in the potential conflicting pattern so as to cut the separate or cutting sections; configuring the double patterning constraint based upon corresponding location relations between each and adjacent cut sections; and assigning a first color layer or a second color layer to the cut sections according to the double patterning constraint to obtain a final layout pattern. Therefore, disadvantageous factors and patterning conflicts caused by separate processes as encountered in the prior art are avoided.

摘要翻译： 提供了一种用于并行迁移和分解适用于双重图案化光刻技术的集成电路布局的方法。 该方法包括切割初始图案的子图案以配置具有分离或切割部分的潜在冲突图案; 去除潜在的冲突图案中的奇数循环，从而切割单独或切割部分; 基于每个相邻切割部分之间的相应位置关系来配置双重图案化约束; 以及根据双重图案化约束将切割部分分配第一颜色层或第二颜色层以获得最终布局图案。 因此，避免了由现有技术中遇到的单独处理引起的不利因素和图案化冲突。

公开(公告)号：US20110003254A1

公开(公告)日：2011-01-06

申请号：US12829437

申请日：2010-07-02

申请人： Yao-Wen Chang ,  Huang-Yu Chen

发明人： Yao-Wen Chang ,  Huang-Yu Chen

IPC分类号： G03F7/20

CPC分类号： G03F7/70466 ,  G03F1/70

摘要： A layout decomposition method, applicable to a double pattern lithography, includes the steps of: putting at least a stitch on each of a plurality of sub-patterns of an initial layout pattern at preset intervals to thereby divide the each of the plurality of sub-patterns into a plurality of unit blocks each selectively labeled as a first region or a second region such that the first region and the second region in same said sub-pattern alternate, wherein any two neighboring ones of said unit blocks attributed to any two neighboring ones of said sub-patterns, respectively, are labeled as the first region and the second region, respectively; reducing the stitches of any two neighboring ones of said unit blocks attributed to any two neighboring ones of said sub-patterns, respectively, so as to generate a first layout pattern having a minimum number of stitches; and reducing the stitches of any two contiguous ones of said unit blocks of each of said sub-patterns in the first layout pattern, so as to generate a second layout pattern having a minimum number of stitches.

摘要翻译： 适用于双模式光刻的布局分解方法包括以下步骤：以预设的间隔将初始布局图案的多个子图案中的每一个以至少一个针迹进行布置，从而将多个子图案中的每一个划分， 模式分成多个单元块，每个单元块选择性地标记为第一区域或第二区域，使得相同的所述子图案中的第一区域和第二区域交替，其中归因于任何两个相邻的单元块中的任何两个相邻单元块 分别标记为第一区域和第二区域; 分别归因于任何两个相邻的子图案的所述单元块中的任何两个相邻的单元块的线圈，以便生成具有最小线数的第一布局图案; 以及减少在所述第一布局图案中的每个所述子图案的所述单元块中的任何两个相邻的所述单元块的针迹，以便生成具有最小线数的第二布局图案。

公开(公告)号：US07799638B2

公开(公告)日：2010-09-21

申请号：US12263091

申请日：2008-10-31

申请人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L21/00

CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  Y10S438/954

摘要： The invention is directed to a method for forming a memory array. The method comprises steps of providing a substrate having a charge trapping structure formed thereon. A patterned material layer is formed over the substrate and the patterned material layer having a plurality of trenches expose a portion of the charge trapping structure. Furthermore, a plurality of conductive spacers are formed on the sidewalls of the trenches of the patterned material layer respectively and a portion of the charge trapping structure at the bottom of the trenches is exposed by the conductive spacers. An insulating layer is formed over the substrate to fill up the trenches of the patterned material layer. Moreover, a planarization process is performed to remove a portion of the insulating layer until a top surface of the patterned material layer and a top surface of each of the conductive spacers are exposed.

摘要翻译： 本发明涉及一种用于形成存储器阵列的方法。 该方法包括提供其上形成有电荷捕获结构的衬底的步骤。 图案化的材料层形成在衬底上，并且具有多个沟槽的图案化材料层暴露电荷俘获结构的一部分。 此外，在图案化材料层的沟槽的侧壁上分别形成多个导电间隔物，并且沟槽底部的电荷捕获结构的一部分被导电间隔物暴露。 在衬底上形成绝缘层以填充图案化材料层的沟槽。 此外，执行平面化处理以去除绝缘层的一部分，直到图案化材料层的顶表面和每个导电间隔物的顶表面露出。

公开(公告)号：US07362122B2

公开(公告)日：2008-04-22

申请号：US11178167

申请日：2005-07-08

申请人： Wei-Cheng Lin ,  Kuo-Pei Lu ,  Yao-Wen Chang

发明人： Wei-Cheng Lin ,  Kuo-Pei Lu ,  Yao-Wen Chang

IPC分类号： G01R31/26

CPC分类号： G01R31/2625 ,  G01R1/44

摘要： A method and a circuit for extracting current-voltage characteristics employ two pulse signals with different duty cycles into a device to be measured in order to extracting current-voltage characteristics of the device to be measured. The present invention may reduce the self-heating effect of the device to be measured and increase the measurable range of the device to be measured.

摘要翻译： 用于提取电流 - 电压特性的方法和电路使用具有不同占空比的两个脉冲信号到待测量的器件中，以便提取待测量器件的电流 - 电压特性。 本发明可以降低要测量的装置的自发热效应，并增加要测量的装置的可测量范围。

公开(公告)号：US20070157146A1

公开(公告)日：2007-07-05

申请号：US11608417

申请日：2006-12-08

申请人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

发明人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

IPC分类号： G06F17/50 ,  H01L25/00 ,  H03K19/00

CPC分类号： G06F17/5072

摘要： A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.

摘要翻译： 多包装树（MPT）宏放样器。 MPT宏放置器包括以LEF / DEF格式读取输入文件，创建包括k个分支节点的k级二进制多重打包树，每个k个分支节点对应于每个对应于一个节点的一个级别和k + 1个打包子树; 包括一组宏，根据其打包结果优化多包装树，并以DEF格式生成输出文件。

公开(公告)号：US06829174B2

公开(公告)日：2004-12-07

申请号：US10248572

申请日：2003-01-30

申请人： Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C700

CPC分类号： G11C16/16 ,  G11C16/10

摘要： A method of narrowing the threshold voltage distribution in a memory. The method includes separating the erase and erase identification of odd memory cells from the erase and erase identification of even memory cells in an advanced non-volatile memory so that the distribution of the threshold voltage is narrowed.

摘要翻译： 缩小存储器中的阈值电压分布的方法。 该方法包括将奇数存储器单元的擦除和擦除识别与高级非易失性存储器中的偶数存储器单元的擦除和擦除识别分离，使得阈值电压的分布变窄。

公开(公告)号：US06624737B2

公开(公告)日：2003-09-23

申请号：US10060376

申请日：2002-02-01

申请人： Yao-Wen Chang ,  Hui-Chih Lin ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Hui-Chih Lin ,  Tao-Cheng Lu

IPC分类号： H01C706

CPC分类号： H01L27/0802 ,  G05F1/46

摘要： This invention relates to a voltage regulated circuit, more particularly, to a voltage regulated circuit with a well resistor divider. The present invention applies two well resistors act as the voltage regulated circuit and uses the characteristic of the well resistor in the resistance value, which is increased following the voltage that is transmitted to the well resistor to make an output voltage become a stable value. When the input voltage is an instable and over-high value, the depletion region in the well resistor will extend to absorb the over-high voltage value and make the output voltage to become a stable voltage value.

摘要翻译： 本发明涉及一种电压调节电路，更具体地说，涉及一种具有阱电阻分压器的电压调节电路。 本发明使用两个阱电阻器作为电压调节电路，并且使用电阻值中的阱电阻器的特性，其随着传输到阱电阻器的电压而增加以使输出电压变为稳定值。 当输入电压为不稳定和过高值时，阱电阻器中的耗尽区域将延伸以吸收过高的电压值，并使输出电压变为稳定的电压值。

公开(公告)号：US06486028B1

公开(公告)日：2002-11-26

申请号：US09990459

申请日：2001-11-20

申请人： Kent Kuohua Chang ,  Yao-Wen Chang

发明人： Kent Kuohua Chang ,  Yao-Wen Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A method for fabricating a nitride read only device is disclosed. A trench is formed in a semiconductor substrate. An ion implantation is performed to form a first source/drain region and a second source/drain region within the substrate in the upper corners of the trench, and to form a common source/drain region within the substrate at a bottom of the trench. Next, a trapping layer is formed over the substrate and the trench and a gate conducting layer is formed over the substrate and filling the trench.

摘要翻译： 公开了一种制造氮化物只读器件的方法。 在半导体衬底中形成沟槽。 执行离子注入以在沟槽的上角中的衬底内形成第一源极/漏极区域和第二源极/漏极区域，并且在沟槽的底部在衬底内形成公共源极/漏极区域。 接下来，在衬底上形成捕获层，并且在衬底上形成沟槽和栅极导电层，并填充沟槽。

公开(公告)号：US6091516A

公开(公告)日：2000-07-18

申请号：US67171

申请日：1998-04-27

申请人： Yao-Wen Chang ,  Che-Yen Lin

发明人： Yao-Wen Chang ,  Che-Yen Lin

IPC分类号： H04N1/10 ,  H04N1/193 ,  H04N1/40

CPC分类号： H04N1/1026 ,  H04N1/1017 ,  H04N1/193 ,  H04N2201/0442 ,  H04N2201/0456

摘要： A contact image sensor is received and held in a holder slidably mounted on a rectangular lower frame and is disposed in parallel to the two short sides of the lower frame to pick up the image of a detection object placed on the transparent plate mounted on a rectangular upper frame. A rod-like guiding member having two ends respectively mounted on the center of the two short sides of the lower frame, disposed orthogonal to the longitudinal holder, for guiding the movement of the holder is provided. A connecting member slidably mounted on the guiding member and detachably connected to the holder near the center thereof is provided. A biasing member for biasing the holder upwardly, disposed between the connecting member and the holder is also provided.

摘要翻译： 接触式图像传感器被接收并保持在可滑动地安装在矩形下框架上的保持架中并且平行于下框架的两个短边设置以拾取放置在安装在矩形上的透明板上的检测对象的图像 上框架 提供了一种杆状引导构件，其具有分别安装在下框架的两个短边的中心处的两个端部，其布置成与纵向保持器正交，用于引导保持器的运动。 设置有可滑动地安装在引导构件上的可拆卸地连接到保持器靠近其中心的连接构件。 还设置有用于将保持器向上偏置并设置在连接构件和保持器之间的偏置构件。