公开(公告)号：US20110004858A1

公开(公告)日：2011-01-06

申请号：US12550484

申请日：2009-08-31

申请人： Yao-Wen Chang ,  Chin-Hsiung Hsu

发明人： Yao-Wen Chang ,  Chin-Hsiung Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for concurrent migration and decomposition of an integrated circuit layout applicable to double patterning lithography techniques is provided. The method includes cutting a sub-pattern of an initial pattern to configure a potentially conflicting pattern having separate or cutting sections; removing odd cycles in the potential conflicting pattern so as to cut the separate or cutting sections; configuring the double patterning constraint based upon corresponding location relations between each and adjacent cut sections; and assigning a first color layer or a second color layer to the cut sections according to the double patterning constraint to obtain a final layout pattern. Therefore, disadvantageous factors and patterning conflicts caused by separate processes as encountered in the prior art are avoided.

摘要翻译： 提供了一种用于并行迁移和分解适用于双重图案化光刻技术的集成电路布局的方法。 该方法包括切割初始图案的子图案以配置具有分离或切割部分的潜在冲突图案; 去除潜在的冲突图案中的奇数循环，从而切割单独或切割部分; 基于每个相邻切割部分之间的相应位置关系来配置双重图案化约束; 以及根据双重图案化约束将切割部分分配第一颜色层或第二颜色层以获得最终布局图案。 因此，避免了由现有技术中遇到的单独处理引起的不利因素和图案化冲突。

公开(公告)号：US08836005B2

公开(公告)日：2014-09-16

申请号：US12862020

申请日：2010-08-24

申请人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L27/108 ,  H01L27/115 ,  H01L21/768 ,  H01L29/423 ,  H01L21/28

CPC分类号： H01L21/28282 ,  H01L21/76885 ,  H01L27/11568 ,  H01L29/4234

摘要： A memory array includes a charge storage structure and a plurality of conductive materials over the charge storage structure is provided. Each conductive material, serving as a word line, has a substantially arc-sidewall and a substantially straight sidewall.

摘要翻译： 存储器阵列包括电荷存储结构，并且提供了电荷存储结构上的多个导电材料。 用作字线的每个导电材料具有基本上弧形的侧壁和基本上直的侧壁。

公开(公告)号：US08759234B2

公开(公告)日：2014-06-24

申请号：US13275021

申请日：2011-10-17

申请人： Yao-Wen Chang ,  Cheng-Yuan Tsai ,  Hsing-Lien Lin

发明人： Yao-Wen Chang ,  Cheng-Yuan Tsai ,  Hsing-Lien Lin

IPC分类号： H01L21/31 ,  C23C16/455 ,  H01L21/28 ,  H01L21/02 ,  C23C16/40 ,  H01L23/485 ,  H01L29/778 ,  H01L29/20 ,  H01L49/02 ,  H01L27/108 ,  H01L29/51

CPC分类号： H01L29/792 ,  C23C16/405 ,  C23C16/45525 ,  H01L21/02107 ,  H01L21/02109 ,  H01L21/02112 ,  H01L21/02175 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28158 ,  H01L21/28176 ,  H01L21/28264 ,  H01L21/30604 ,  H01L21/30612 ,  H01L23/485 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/40 ,  H01L28/60 ,  H01L29/20 ,  H01L29/205 ,  H01L29/365 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/6656 ,  H01L29/7783 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

摘要翻译： 提供一种用于制造半导体器件的系统和方法。 一个实施例包括使用原子层沉积（ALD）工艺形成沉积层。 ALD过程可以利用第一时间段的第一前体，比第一时间段长的第二时间段的第一次净化，第三时间段比第一时间段长的第二前体， 第四个时间段长于第三个时间段。

公开(公告)号：US08462773B2

公开(公告)日：2013-06-11

申请号：US13152288

申请日：2011-06-03

申请人： Yao-Wen Chang

发明人： Yao-Wen Chang

IPC分类号： H04L12/66

CPC分类号： H04L61/106 ,  H04L61/1511 ,  H04L61/2076 ,  H04L61/305 ,  H04L65/1069 ,  H04M7/1255 ,  H04M7/128

摘要： A terminal device receives a called telephone number inputted by a user. The terminal device generates a called domain name corresponding to the called telephone number according to a predefined rule, and queries the DDNS server for a called IP address that corresponds to the called domain name. The terminal device exchanges VoIP signaling with a called terminal device according to the called IP address when the called IP address is successfully queried from the DDNS server.

摘要翻译： 终端装置接收用户输入的被叫电话号码。 终端设备根据预定义规则生成对应于被叫电话号码的被叫域名，并向DDNS服务器查询与被叫域名对应的被叫IP地址。 当从DDNS服务器成功查询被叫IP地址时，终端设备根据被叫IP地址与被叫终端设备进行VoIP信令交换。

公开(公告)号：US08411506B2

公开(公告)日：2013-04-02

申请号：US12949076

申请日：2010-11-18

申请人： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L29/66

CPC分类号： H01L21/28282 ,  G11C16/0475 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/7923

摘要： A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulation layer. The first and second doped regions are disposed in the substrate and extend along a first direction. The first and second doped regions are arranged alternately. The charged-trapping structure is disposed on the substrate. The first and second gates are disposed on the charged-trapping structure. Each first gate is located above one of the first doped regions. The second gates extend along a second direction and are located above the second doped regions. The inter-gate insulation layer is disposed between the first gates and the second gates. Adjacent first and second doped regions and the first gate, the second gate and the charged-trapping structure therebetween define a memory cell.

摘要翻译： 提供一种非易失性存储器及其制造方法以及操作存储单元的方法。 非易失性存储器包括衬底，第一和第二掺杂区域，带电捕获结构，第一和第二栅极以及栅极间绝缘层。 第一和第二掺杂区域设置在衬底中并沿着第一方向延伸。 第一和第二掺杂区交替布置。 带电捕获结构设置在基板上。 第一和第二栅极设置在带电捕获结构上。 每个第一栅极位于第一掺杂区域之上。 第二栅极沿着第二方向延伸并且位于第二掺杂区域之上。 栅间绝缘层设置在第一栅极和第二栅极之间。 相邻的第一和第二掺杂区域和第一栅极，其间的第二栅极和带电捕获结构限定了存储单元。

公开(公告)号：US08340141B2

公开(公告)日：2012-12-25

申请号：US13489417

申请日：2012-06-05

申请人： Yao-Wen Chang ,  Chien-Ming Huang

发明人： Yao-Wen Chang ,  Chien-Ming Huang

IPC分类号： H01S3/00

CPC分类号： H01S3/06791 ,  H01S3/06725 ,  H01S3/094076 ,  H01S3/1061 ,  H01S3/1118 ,  H01S3/1618

摘要： A method of operating an all-fiber-based ultra short pulse laser system is provided. The steps includes providing an all-fiber-based ultra short pulse laser system having a pulse pump light source, a fiber saturable absorber, an assistant light source, at least a dispersion fiber, and a light coupling output; generating a broadband ASE via the pulse pump light source; making the all-fiber-based ultra short pulse laser system switch passive mode locking via the fiber saturable absorber; decreasing the restoring period of the fiber saturable absorber via the assistant light source; providing dispersion compensation via the dispersion fiber to output an ultra short pulse; and partially outputting a laser passing through the all-fiber-based ultra short pulse laser system via the light coupling output.

摘要翻译： 提供了一种操作全光纤超短脉冲激光系统的方法。 这些步骤包括提供具有脉冲泵浦光源的全光纤超短脉冲激光系统，光纤饱和吸收器，辅助光源，至少分散光纤和光耦合输出; 通过脉冲泵浦光源产生宽带ASE; 使全光纤超短脉冲激光系统通过光纤可饱和吸收器切换被动模式锁定; 通过辅助光源减少光纤可饱和吸收体的恢复周期; 通过色散光纤提供色散补偿以输出超短脉冲; 并且经由光耦合输出部分地输出通过全光纤的超短脉冲激光系统的激光。

公开(公告)号：US20120261739A1

公开(公告)日：2012-10-18

申请号：US13088240

申请日：2011-04-15

申请人： I-CHEN YANG ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： I-CHEN YANG ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7881 ,  H01L29/42336 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/7834

摘要： A semiconductor device including a first doped region of a first conductivity type, a second doped region of a second conductivity type, a gate, and a dielectric layer is provided. The first doped region is located in a substrate and has a trench. The second doped region is located at the bottom of the trench to separate the first doped region into a source doped region and a drain doped region. A channel region is located between the source doped region and the drain doped region. The gate is located in the trench. The dielectric layer covers the sidewall and the bottom of the trench and separates the gate and the substrate.

摘要翻译： 提供包括第一导电类型的第一掺杂区域，第二导电类型的第二掺杂区域，栅极和介电层的半导体器件。 第一掺杂区域位于衬底中并且具有沟槽。 第二掺杂区域位于沟槽的底部，以将第一掺杂区域分离成源掺杂区域和漏极掺杂区域。 沟道区位于源极掺杂区和漏极掺杂区之间。 门位于沟槽中。 电介质层覆盖沟槽的侧壁和底部并分离栅极和衬底。

公开(公告)号：US08261223B2

公开(公告)日：2012-09-04

申请号：US13093814

申请日：2011-04-25

申请人： Meng-Kai Hsu ,  Yao-Wen Chang ,  Tung-Chieh Chen

发明人： Meng-Kai Hsu ,  Yao-Wen Chang ,  Tung-Chieh Chen

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5072

摘要： A placer produces a global placement plan specifying positions of cell instances and orientations of macros within an integrated circuit (IC) by initially clusterizing cell instances and macros to form a pyramidal hierarchy of blocks. Then the placer iteratively repeats the declusterization and routability improvement process from the highest level to the lowest level of the hierarchy. An objective function is provided in Cartesian coordinate for representing the position of each movable instance and in polar coordinate for representing the orientation of a macro relative to its the center. For each movable instance and each rotatable macro, its position or orientation is determined by conjugate gradient method to minimize total wire length. Finally, the placer uses a look-ahead legalization technique to rotate rotatable macros to legal orientations and move cell instances to legal positions in the end of global placement.

摘要翻译： 放样器通过最初将单元实例和宏聚类以形成块的锥体层次，产生一个全局放置计划，指定集成电路（IC）中宏的位置和宏的位置。 然后，迭代器迭代地重复从层次结构的最高级别到最低级别的分解和路由改进过程。 在笛卡尔坐标中提供了一个目标函数，用于表示每个可移动实例的位置，并以极坐标表示宏相对于其中心的方向。 对于每个可移动实例和每个可旋转宏，其位置或取向由共轭梯度法确定，以使总线长度最小化。 最后，Placer使用先行合法化技术将可旋转的宏转换为法定方向，并在全局放置结束时将单元格实例移动到合法位置。

公开(公告)号：US08248937B2

公开(公告)日：2012-08-21

申请号：US12763148

申请日：2010-04-19

申请人： Kai-Yu Yang ,  Yao-Wen Chang

发明人： Kai-Yu Yang ,  Yao-Wen Chang

IPC分类号： G01R31/08

CPC分类号： H04L47/29 ,  H04L47/125

摘要： A packet forwarding device stores a predetermined threshold and a predetermined condition value of a first wide area network (WAN) port, and forwards packets that comply with the predetermined condition value via the first WAN port and forwards packets that do not comply with the predetermined condition value via a second WAN port. The packet forwarding device forwards some of the packets that do not comply with the predetermined condition value via the first WAN port in order to balance loads of the first and second WAN ports if the traffic value of the packets forwarded via the first WAN port is equal to or less than the predetermined threshold.

摘要翻译： 分组转发装置存储第一广域网（WAN）端口的预定阈值和预定条件值，并且经由第一WAN端口转发符合预定条件值的分组，并转发不符合预定条件的分组 通过第二个WAN端口的值。 如果通过第一WAN端口转发的分组的流量值相等，则分组转发设备经由第一WAN端口转发不符合预定条件值的一些分组，以便平衡第一和第二WAN端口的负载 达到或小于预定阈值。

公开(公告)号：US08228727B2

公开(公告)日：2012-07-24

申请号：US12623110

申请日：2009-11-20

申请人： Yuan-Peng Chao ,  Yao-Wen Chang

发明人： Yuan-Peng Chao ,  Yao-Wen Chang

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C11/5621

摘要： A method for programming a multi-level cell and a memory apparatus are described, wherein each cell has two storage sites. The method includes making the first storage site have a first Vt level and the second storage site have a second Vt level. The first Vt level is selected from M Vt levels. When the first Vt level is the i-th level among the M Vt levels, the second Vt level is selected from ni Vt levels, wherein at least one ni is not equal to ni-1 (2≦i≦M). The multi-level cell has P storage states, wherein P = ∑ i = 1 M ⁢ ⁢ n i . The memory apparatus includes multiple multi-level cells and an operation circuit capable of performing the above method.

摘要翻译： 描述了一种用于编程多级单元和存储装置的方法，其中每个单元具有两个存储位置。 所述方法包括使所述第一存储站点具有第一Vt级别，并且所述第二存储站点具有第二Vt级别。 第一个Vt级别从M Vt级别中选择。 当第一Vt电平是M Vt电平中的第i电平时，第二Vt电平选自niVt电平，其中至少一个ni不等于ni-1（2＆nlE; i＆nlE; M）。 多级单元具有P个存储状态，其中P =Σi = 1 M 存储装置包括多个多电平单元和能够执行上述方法的操作电路。