公开(公告)号：US5745420A

公开(公告)日：1998-04-28

申请号：US833582

申请日：1997-04-07

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/18 ,  G11C29/50 ,  G11C7/00

CPC classification number: G11C7/18 ,  G11C29/50 ,  G11C11/41

Abstract: An integrated circuit having a memory array comprised of a plurality of memory cells arranged in rows and columns and a logic circuitry including column decoder and read/write circuitry, wherein each column includes a plurality of memory cells connected in parallel by way of a pair of true and complement bitlines extending from the memory array to the logic circuitry. In order to perform a complete voltage stress test of the memory array, inside the array true and complement bitlines are alternated so that every true bitline is adjacent exclusively to complement bitlines and every complement bitline is adjacent exclusively to true bitlines. According to a first embodiment of the invention, bitlines exiting from the memory array are connected directly to the logic circuitry, while according to a second embodiment, between the array and the logic circuitry, at least one pair of true and complement bitlines is twisted so that one bitline cross over the other. As a result, inside the memory array the true bitline of said at least one pair is adjacent exclusively to complement bitlines and the complement bitline of said at least one pair is adjacent exclusively to true bitlines.

Abstract translation: 一种集成电路，具有由排列成行和列的多个存储单元组成的存储器阵列和包括列解码器和读/写电路的逻辑电路，其中每列包括多个存储单元，所述存储单元通过一对 从存储器阵列延伸到逻辑电路的真实和补码位线。 为了执行存储器阵列的完整的电压应力测试，阵列内部的真和补码位线被交替，使得每个真正的位线仅与补充位线相邻，并且每个补码位线仅与真位线相邻。 根据本发明的第一实施例，从存储器阵列退出的位线直接连接到逻辑电路，而根据第二实施例，在阵列与逻辑电路之间，至少一对真和补码位线被扭转 一个位线交叉在另一个。 结果，在存储器阵列内部，所述至少一对的真正位线仅与补码位线相邻，并且所述至少一对的补码位线仅与真位线相邻。

公开(公告)号：US5657292A

公开(公告)日：1997-08-12

申请号：US588662

申请日：1996-01-19

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/00 ,  G11C7/10 ,  G11C8/00

CPC classification number: G11C7/1057 ,  G11C7/00 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078

Abstract: A write global bus driver is provided within the data input buffer. The write global bus driver has the same circuit configuration as the read global bus driver so that it drives the output buffer with the very same type of signal and in the same way as the read global bus driver drives the output buffer. The write global bus driver is coupled to the global data bus for placing written data on the global data bus that is normally used only for read data. During each write cycle, the data is written simultaneously to the memory array and to the output buffer. The output buffer is a two-stage, pipelined output buffer. When data is stored in the first stage of the output buffer, whether write data or read data, it is maintained in the first stage on the same clock cycle that it is presented. On the subsequent clock cycle, the data from the first stage is transferred to the second stage and is provided as the output of the output buffer. In the event a read cycle immediately follows a write cycle, the write data is provided as the output from the output buffer as a result of the first read cycle being performed. During the second read cycle, the data read during the first read cycle is provided as the output.

Abstract translation: 在数据输入缓冲器中提供写全局总线驱动器。 写全局总线驱动器具有与读取的全局总线驱动器相同的电路配置，从而以与读取的全局总线驱动器驱动输出缓冲器相同的方式驱动具有相同类型的信号的输出缓冲器。 写全局总线驱动器耦合到全局数据总线，用于将通常仅用于读取数据的全局数据总线上的写入数据放置。 在每个写周期期间，数据被同时写入存储器阵列和输出缓冲器。 输出缓冲区是两级流水线输出缓冲区。 当数据存储在输出缓冲器的第一级中时，无论是写入数据还是读取数据，都将以与其呈现的相同的时钟周期保持在第一级。 在随后的时钟周期中，来自第一级的数据被传送到第二级，并被提供作为输出缓冲器的输出。 在读周期紧随着写周期的情况下，作为执行第一读周期的结果，写数据被提供为来自输出缓冲器的输出。 在第二读取周期期间，在第一读取周期期间读取的数据被提供作为输出。

公开(公告)号：US5640122A

公开(公告)日：1997-06-17

申请号：US464551

申请日：1995-06-05

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G05F3/20 ,  G05F3/26 ,  H02J1/00

CPC classification number: G05F3/205 ,  G05F3/262

Abstract: A bias circuit for generating a bias voltage that tracks power supply voltage variations, and that is compensated for variations in p-channel transistor and process parameters, is disclosed. The bias circuit includes a voltage divider, such as a resistor divider, that produces a ratioed voltage based on the power supply voltage to be tracked. The ratioed voltage is applied to a first input of a differential stage, the output of which is applied to an intermediate stage including a drive transistor and a load; the second input of the differential stage receives a feedback voltage from an intermediate node that is connected to the source of a p-channel modulating transistor that has its gate biased so as to be in saturation, for example at ground. The current conducted by the p-channel modulating transistor depends upon the ratioed voltage from the voltage divider, and also on its transistor characteristics. This current is applied, via an output stage, to produce a reference voltage that tracks power supply voltage variations. This reference voltage may be applied, individually or in combination with an n-channel compensated reference voltage, to an output buffer to control output drive slew rates, or to a current source.

Abstract translation: 公开了一种用于产生跟踪电源电压变化并且被补偿了p沟道晶体管和工艺参数中的变化的偏置电压的偏置电路。 偏置电路包括诸如电阻器分压器的分压器，其基于待跟踪的电源电压产生比率电压。 将比率电压施加到差分级的第一输入，其输出被施加到包括驱动晶体管和负载的中间级; 差分级的第二输入接收来自中间节点的反馈电压，该中间节点连接到其栅极偏置为饱和的p沟道调制晶体管的源，例如在地。 由p沟道调制晶体管传导的电流取决于来自分压器的比例电压，以及其晶体管特性。 该电流经由输出级施加以产生跟踪电源电压变化的参考电压。 该参考电压可以单独地或与n沟道补偿参考电压组合施加到输出缓冲器以控制输出驱动转换速率，或者施加到电流源。

公开(公告)号：US5633828A

公开(公告)日：1997-05-27

申请号：US519075

申请日：1995-08-24

Applicant: David C. McClure ,  Mark A. Lysinger ,  Frank J. Sigmund ,  John A. Michlowsky

Inventor： David C. McClure ,  Mark A. Lysinger ,  Frank J. Sigmund ,  John A. Michlowsky

IPC: G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C29/14 ,  G11C29/30 ,  G11C7/00

CPC classification number: G11C29/30 ,  G11C29/04

Abstract: According to the present invention, a structure and method provides for single bit failures of an integrated circuit memory device to be analyzed. According to the method for analyzing a single bit failure of an integrated circuit memory device, a test mode is entered, bitline load devices of the integrated circuit memory device are turned off, a single bit of the integrated circuit memory device is selected, the device is placed into a write mode, a plurality of bitlines true and a plurality of bitlines complement of the integrated circuit memory device not associated with the single bit are then set to a low logic level, the bitline true and the bitline complement associated with the single bit is connected to a supply bus and a supply complement bus which is connected to test pads. Finally, the electrical characteristics of the single bit can be monitored on the test pads. According to the structure of the present invention, bitline load devices of the integrated circuit memory device are controlled by a test mode signal, the state of which determines when the test mode will be entered. These bitline load devices are connected to the bitlines true and complement which in turn are connected to the memory cell. Select devices, such as column select transistors, are connected to the bitline true and bitline complement; they are also connected to driver circuitry by a bus, such as a write bus, a read bus or a write/read bus. The driver circuitry is supplied with supply voltages as well as data signals. Further, a buffer circuit allows bitlines true and bitlines complement not associated with the single bit being tested to be pulled to a logic low level. A dummy structure also provides the opportunity to directly monitor the bitlines of the integrated circuit memory device without the need for microprobing.

Abstract translation: 根据本发明，结构和方法提供要分析的集成电路存储器件的单位故障。 根据用于分析集成电路存储器件的单位故障的方法，输入测试模式，集成电路存储器件的位线负载器件被截止，选择集成电路存储器件的单位，器件 被放置在写入模式中，然后将多个位线true和不与单个位相关联的集成电路存储器件的多个位线补码设置为低逻辑电平，与单个位相关联的位线真和位线补码 位连接到连接到测试焊盘的电源总线和电源补充总线。 最后，可以在测试焊盘上监视单个位的电气特性。 根据本发明的结构，集成电路存储器件的位线负载装置由测试模式信号控制，其状态决定了何时进入测试模式。 这些位线负载装置连接到位线和真正的补码，而补码又连接到存储单元。 选择器件，如列选择晶体管，连接到位线真和位线补码; 它们也通过总线连接到驱动器电路，例如写总线，读总线或写/读总线。 驱动器电路提供电源电压以及数据信号。 此外，缓冲电路允许位线为真，并且与待测试的单个位相关联的位线补码被拉至逻辑低电平。 虚拟结构还提供了直接监视集成电路存储器件的位线的机会，而不需要微阵列。

公开(公告)号：US5627793A

公开(公告)日：1997-05-06

申请号：US413789

申请日：1995-03-30

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/41 ,  G11C7/06 ,  G11C7/22 ,  G11C11/417 ,  H01L27/10 ,  G11C13/00

CPC classification number: G11C7/22 ,  G11C7/06

Abstract: A method and circuit for significantly reducing a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device. An output of a first circuit is connected to a data line. The first circuit is designed with elements having a selected set of design parameters, such as transistor dimensions and transistor orientation. A second circuit is connected to the data line and also receives a clock signal generated by a signal delay circuit. The signal delay circuit receives an output enable signal, and after a delay period, produces the clock signal in response to the output enable signal. At least a portion of the signal delay circuit utilizes elements having the selected set of design parameters utilized in the first circuit. Thus, as process variations affect the electrical properties and the speed of the transistors in the first circuit, the same process variations will proportionately affect the electrical properties and speed of transistors in the delay circuit. This automatically compensates for process-induced speed variations and eliminates the need for a time margin when providing a clock signal for clocking an output of a first circuit into the input of a second circuit.

Abstract translation: 一种用于显着减少添加到时钟信号中的延迟的方法和电路，所述时钟信号将第一电路的输出定时成半导体器件中的第二电路的输入。 第一电路的输出连接到数据线。 第一电路设计有具有选定的一组设计参数的元件，例如晶体管尺寸和晶体管取向。 第二电路连接到数据线，并且还接收由信号延迟电路产生的时钟信号。 信号延迟电路接收输出使能信号，并且在延迟周期之后，响应于输出使能信号产生时钟信号。 信号延迟电路的至少一部分利用在第一电路中使用的具有所选择的一组设计参数的元件。 因此，随着工艺变化影响第一电路中的晶体管的电性能和速度，相同的工艺变化将成比例地影响延迟电路中的晶体管的电性能和速度。 这自动补偿过程引起的速度变化，并且当提供用于将第一电路的输出计时到第二电路的输入的时钟信号时，不需要时间裕度。

公开(公告)号：US5612918A

公开(公告)日：1997-03-18

申请号：US582424

申请日：1995-12-29

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

CPC classification number: G11C29/785 ,  G11C29/24 ,  G11C29/80 ,  G11C29/808 ,  G11C29/84

Abstract: A redundancy structure having fewer pass gates in the redundant decoder for quicker access to a redundant columns and a reduction in the complexity of the redundancy structure.

Abstract translation: 在冗余解码器中具有较少传输门的冗余结构，用于更快地访问冗余列并降低冗余结构的复杂度。

公开(公告)号：US5594373A

公开(公告)日：1997-01-14

申请号：US359397

申请日：1994-12-20

Applicant: David C. McClure

Inventor： David C. McClure

IPC: H03K19/0175 ,  G05F1/46 ,  G11C11/407 ,  H03K19/0185 ,  H03K19/0948 ,  H03B21/00

CPC classification number: H03K19/018585 ,  G05F1/465

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses. An offset compensating current source adds current into the reference leg of the current mirror to eliminate the development of an offset voltage in the current mirror, and the limited output high voltage is shifted by the threshold voltage of the pull-up drive transistor by way of a threshold shift circuit.

Abstract translation: 公开了一种用于集成电路的输出驱动器电路，其中输出驱动器驱动具有从集成电路的电源电压限制的电压的高逻辑电平的输出端子。 通过将有限的输出高电压施加到输出缓冲器来提供有限的电压，使得施加到输出驱动器中的上拉晶体管的栅极的驱动信号受到施加到输出缓冲器的受限输出高电压的限制。 还公开了用于产生有限输出高电压的电压基准和调节器电路，并且基于电流镜。 电流镜中的电流总和由偏置电流源控制，偏置电流源可以在运行周期内动态控制或通过熔丝进行编程。 偏移补偿电流源将电流加到电流镜的参考支路中，以消除电流镜中偏移电压的发展，并且受限输出高电压通过上拉驱动晶体管的阈值电压偏移 阈值移位电路。

公开(公告)号：US5590307A

公开(公告)日：1996-12-31

申请号：US711

申请日：1993-01-05

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G06F12/08 ,  G11C8/16 ,  G11C11/401 ,  G11C11/41

CPC classification number: G06F12/0853 ,  G06F12/0879 ,  G11C8/16

Abstract: A dual-port data cache is provided having one port dedicated to servicing a local processor and a second port dedicated to servicing a system. The dual-port data cache is also capable of a high speed transfer of a line or lines of entries by placing the dual-port data cache in "burst mode." Burst mode may be utilized with either a read or a write operation. An initial address is latched internally, and a word line in the memory array is activated during the entire data transfer. A control circuit is utilized to cycle through and access a number of column addresses without having to provide a separate address for each operation.

Abstract translation: 提供双端口数据高速缓存，其具有专用于服务本地处理器的一个端口和专用于维护系统的第二端口。 通过将双端口数据高速缓存置于“突发模式”中，双端口数据高速缓存还能够高速传输一行或多条条目。 可以在读取或写入操作中使用突发模式。 初始地址在内部被锁存，并且在整个数据传输期间，存储器阵列中的字线被激活。 利用控制电路来循环访问多个列地址，而不必为每个操作提供单独的地址。

公开(公告)号：US5589783A

公开(公告)日：1996-12-31

申请号：US282177

申请日：1994-07-29

Applicant: David C. McClure

Inventor： David C. McClure

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/0948

CPC classification number: H03K19/018585 ,  H03K19/0027

Abstract: According to the present invention, an integrated circuit device is capable of responding to more than one input threshold voltage level by making only minimal changes to the device. The input buffer of the integrated circuit device is modified to be a programmable buffer that is controlled by a control input signal which may be generated by several different control means. Such control means include a bond option, a mask option, a fuse option, a register option, and a voltage detector option.

Abstract translation: 根据本发明，集成电路器件能够通过对器件进行最小的改变来响应多于一个的输入阈值电压电平。 集成电路装置的输入缓冲器被修改为可由可由若干不同控制装置产生的控制输入信号控制的可编程缓冲器。 这种控制装置包括接合选项，掩模选项，熔丝选项，寄存器选项和电压检测器选项。

公开(公告)号：US5577051A

公开(公告)日：1996-11-19

申请号：US173197

申请日：1993-12-22

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C29/02 ,  G11C29/50 ,  G11C29/00

CPC classification number: G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C11/41

Abstract: According to the present invention, after a test data pattern has been written to selected static memory cells, the wordlines of the memory cells are turned off and the bitline true and bitline complement of the memory cells are simultaneously pulled to a predetermined logic level for the duration of the long write test so that the memory cells are disturbed. After the long write test, the contents of the memory cells are read to determine which memory cells contain corrupted data and therefore have bitline to memory cell leakage problems.

Abstract translation: 根据本发明，在将测试数据模式写入所选择的静态存储单元之后，关闭存储单元的字线，并将存储单元的位线真和位线补码同时拉至预定的逻辑电平 长写入测试的持续时间，使得存储器单元受到干扰。 在长写入测试之后，读取存储器单元的内容以确定哪些存储器单元包含损坏的数据，因此具有存储单元泄漏问题的位线。